WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 323

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
10.2.4.4
Interrupt Cause Set Register - ICS (0x000C8; W)
Software uses this register to set an interrupt condition. Any bit written with a 1b sets
the corresponding interrupt. This results in the corresponding bit being set in the
Interrupt Cause Read register (see
generated if one of the bits in this register is set and the corresponding interrupt is
enabled via the Interrupt Mask Set/Read register (see
Bits written with 0b are unchanged.
TXDW
TXQE
LSC
Reserved
RXDMT0
Reserved
RXO
RXT0
reserved
MDAC
Reserved
Reserved
Reserved
Reserved
TXD_LOW
SRPD
ACK
MNG
Reserved
RxQ0
RxQ1
TxQ0
TxQ1
Other
Reserved
Field
0
1
2
3
4
5
6
7
8
9
10
11
12
14:13
15
16
17
18
19
20
21
22
23
24
31:25
Bit(s)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
X
Initial
Value
Sets Transmit Descriptor Written Back
Sets Transmit Queue Empty
Sets Link Status Change.
Reserved
Sets Receive Descriptor Minimum Threshold Hit
Reserved
Sets Receiver Overrun
Set on receive data FIFO overrun.
Sets Receiver Timer Interrupt
Reserved
Sets MDIO Access Complete Interrupt
Reserved
Reserved
Reserved
Reserved
Transmit Descriptor Low Threshold Hit
Small Receive Packet Detected and Transferred
Sets Receive ACK Frame Detected
Sets Manageability Event
Reserved
Sets Receive Queue 0 Interrupt
Sets Receive Queue 1 Interrupt
Sets Transmit Queue 0 Interrupt
Sets Transmit Queue 1 Interrupt
Sets Other Interrupt
Reserved
Should be written with 0x0 to ensure future compatibility
Section
10.2.4.1). A PCIe interrupt is also
Description
Section
10.2.4.5).
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