WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 80

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
4.6.4
4.6.5
80
Since both CTRL.SLU and the PHY link indication LINK are forced, this bit set does not
guarantee that operation of the link has been truly established.
Initialization of Statistics
Statistics registers are hardware-initialized to values as detailed in each particular
register's description. The initialization of these registers begins at transition to D0
active power state (when internal registers become accessible, as enabled by setting
the Memory Access Enable field of the PCIe Command register), and is guaranteed to
complete within 1 ms of this transition. Access to statistics registers prior to this
interval might return indeterminate values.
All of the statistical counters are cleared on read and a typical software device driver
reads them (thus making them zero) as a part of the initialization sequence.
Receive Initialization
Program the receive address register(s) per the station address. This can come from
the NVM or from any other means, for example, on some systems, this comes from the
system EEPROM not the NVM on a Network Interface Card (NIC).
Set up the Multicast Table Array (MTA) per software. This generally means zeroing all
entries initially and adding in entries as requested.
Program the interrupt mask register to pass any interrupt that the software device
driver cares about. Suggested bits include RXT, RXO, RXDMT and LSC. There is no
reason to enable the transmit interrupts.
Program RCTL with appropriate values. If initializing it at this stage, it is best to leave
the receive logic disabled (EN = 0b) until the receive descriptor ring has been
initialized. If VLANs are not used, software should clear the VFE bit. Then there is no
need to initialize the VFTA array. Select the receive descriptor type. Note that if using
the header split RX descriptors, tail and head registers should be incremented by two
per descriptor.
• MAC/PHY duplex and speed settings both forced by software (fully-forced
link setup). (CTRL.FRCDPLX = 1b, CTRL.FRCSPD = 1b, CTRL.SLU = 1b)
— CTRL.FD - Set by software to desired full-/half- duplex operation (must match
— CTRL.SLU - Must be set to 1b by software to enable communications between
— CTRL.RFCE - Must be set by software to the desired flow-control operation
— CTRL.TFCE - Must be set by software to the desired flow-control operation
— CTRL.SPEED - Set by software to desired link speed (must match speed setting
— STATUS.FD - Reflects the MAC duplex setting written by software to CTRL.FD.
— STATUS.LU - Reflects 1b (positive link indication LINK from PHY qualified with
— STATUS.SPEED - Reflects MAC forced speed setting written in CTRL.SPEED.
duplex setting of the PHY).
the MAC and PHY. The PHY must also be forced/configured to indicate positive
link indication (LINK) to the MAC.
(must match flow-control settings of the PHY).
(must match flow-control settings of the PHY).
of the PHY).
CTRL.SLU).
82574 GbE Controller—Initialization