WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 452

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.5.5.12
13.5.5.13
13.5.6
13.5.6.1
13.5.7
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Traces for Decoupling Capacitors
Traces between decoupling and I/O filter capacitors should be as short and wide as
practical. Long and thin traces are more inductive and would reduce the intended effect
of decoupling capacitors. Also for similar reasons, traces to I/O signals and signal
terminations should be as short as possible. Vias to the decoupling capacitors should be
sufficiently large in diameter to decrease series inductance.
Light Emitting Diodes for Designs Based on the 82574
The 82574L provides three programmable high-current push-pull (active high) outputs
to directly drive LEDs for link activity and speed indication. Each LAN device provides
an independent set of LED outputs; these pins and their function are bound to a specific
LAN device. Each of the four LED outputs can be individually configured to select the
particular event, state, or activity, which is indicated on that output. In addition, each
LED can be individually configured for output polarity, as well as for blinking versus
non-blinking (steady-state) indication.
Since the LEDs are likely to be integral to a magnetics module, take care to route the
LED traces away from potential sources of EMI noise. In some cases, it may be
desirable to attach filter capacitors.
The LED ports are fully programmable through the NVM interface.
Physical Layer Conformance Testing
Physical layer conformance testing (also known as IEEE testing) is a fundamental
capability for all companies with Ethernet LAN products. PHY testing is the final
determination that a layout has been performed successfully. If your company does not
have the resources and equipment to perform these tests, consider contracting the
tests to an outside facility.
Conformance Tests for 10/100/1000 Mb/s Designs
Crucial tests are as follows, listed in priority order:
Troubleshooting Common Physical Layout Issues
The following is a list of common physical layer design and layout mistakes in LAN On
Motherboard Designs.
1. Lack of symmetry between the two traces within a differential pair. Asymmetry can
2. Unequal length of the two traces within a differential pair. Inequalities create
• Bit Error Rate (BER). Good indicator of real world network performance. Perform bit
• Output Amplitude, Rise and Fall Time (10/100 Mb/s), Symmetry and Droop
• Return Loss. Indicator of proper impedance matching, measured through the RJ-45
• Jitter Test (10/100 Mb/s) or Unfiltered Jitter Test (1000 Mb/s). Indicator of clock
error rate testing with long and short cables and many link partners. The test limit
is 10
(1000Mbps). For the 82575 controller, use the appropriate PHY test waveform.
connector back toward the magnetics module.
recovery ability (master and slave for Gigabit controller).
create common-mode noise and distort the waveforms. For each component and/or
via that one trace encounters, the other trace should encounter the same
component or a via at the same distance from the Ethernet silicon.
common-mode noise and will distort the transmit or receive waveforms.
-11
errors.
82574 GbE Controller—Design Considerations