WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 129

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
Note:
7.1.2
Note:
7.1.3
Good packets are defined as those packets with no:
However, if the Store-Bad-Packet bit is set in the Device Control register (RCTL.SBP),
then bad packets that pass the filter function are stored in host memory. Packet errors
are indicated by error bits in the receive descriptor (RDESC.ERRORS). It is possible to
receive all packets, regardless of whether they are bad, by setting the promiscuous
enables and the Store-Bad-Packet bit.
CRC errors before the SFD are ignored. Every packet must have a valid SFD (RX_DV
with no RX_ER in the GMII/MII interface) in order to be recognized by the device (even
bad packets).
Receive Data Storage
Memory buffers pointed to by descriptors store packet data. Hardware supports the
following receive buffer sizes:
Buffer size is selected by bit settings in the Receive Control register (RCTL.BSIZE,
RCTL.BSEX, RCTL.DTYP and RCTL. FLXBUF).
The 82574L (in legacy mode) places no alignment restrictions on receive memory
buffer addresses. This is desirable in situations where the receive buffer was allocated
by higher layers in the networking software stack, as these higher layers might have no
knowledge of a specific device's buffer alignment requirements.
Although alignment is completely unrestricted, it is highly recommended that software
allocate receive buffers on at least cache-line boundaries whenever possible.
Legacy Receive Descriptor Format
A receive descriptor is a data structure that contains the receive data buffer address
and fields for hardware to store packet information. If the RFCTL.EXSTEN bit is clear
and the RCTL.DTYP equals 00b, the 82574 uses the Legacy Rx Descriptor as shown in
the following figure.
• CRC error
• Symbol error
• Sequence error
• Length error
• Alignment error
• Where carrier extension or RX_ERR errors are detected.
• 256B
• FLXBUF x 1024B while FLXBUF=1,2,3,…15
512B
1024B
2048B
4096B
8192B
16384B
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