WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 320

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.4
10.2.4.1
320
Interrupt Register Descriptions
Interrupt Cause Read Register - ICR (0x000C0; RC/WC)
TXDW
TXQE
LSC
Reserved
RXDMT0
Reserved
RXO
RXT0
Reserved
MDAC
Reserved
TXD_LOW
SRPD
Flow control DLLP received in link layer.
Ack DLLP received.
Nack DLLP received.
Field
Link Layer Events
0
1
2
3
4
5
6
7
8
9
14:10
15
16
Bit(s)
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0x0
0b
0b
Initial
Value
Transmit Descriptor Written Back
Set when hardware processes a descriptor with RS set. If using
delayed interrupts (IDE set), the interrupt is delayed until after one of
the delayed-timers (TIDV or TADV) expires.
Transmit Queue Empty
Set when the last descriptor block for a transmit queue has been
used. When configured to use more than one transmit queue this
interrupt indication is issued if one of the queues is empty and is not
cleared until all the queues have valid descriptors.
Link Status Change
This bit is set whenever the link status changes (either from up to
down, or from down to up). This bit is affected by the link indication
from the PHY.
Reserved
Receive Descriptor Minimum Threshold Hit.
This bit indicates that the number of receive descriptors has reached
the minimum threshold as set in RCTL.RDMTS. This indicates to the
software to load more receive descriptors.
Reserved
Receiver Overrun
Set on receive data FIFO overrun. Could be caused either because
there are no available buffers or because PCIe receive bandwidth is
inadequate.
Receiver Timer Interrupt
Set when the timer expires.
Reserved
MDIO Access Complete
Set when MDIO access completes. See
Reserved
Transmit Descriptor Low Threshold Hit
Indicates that the number of descriptors in the transmit descriptor
ring has reached the level specified in the Transmit Descriptor Control
register (TXDCTL.LWTHRESH).
Small Receive Packet Detected
Indicates that a packet of size < RSRPD.SIZE has been detected and
transferred to host memory. The interrupt is only asserted if
RSRPD.SIZE register has a non-zero value.
56
57
58
Mapping
Event
82574 GbE Controller—Driver Programing Interface
Each cycle, the counter increases by 1, if message
was received.
Each cycle, the counter increases by 1, if message
was received.
Each cycle, the counter increases by 1, if message
was transmitted.
Description
Description
Section 10.2.7.36
for details.