WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 195

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
7.7.4
After offset calculation the system time register should be updated. This is done by
writing the calculated offset to TIMADJL and TIMADJH registers. The order should be as
follows:
After the write cycle to TIMADJH the value of TIMADJH and TIMADJL should be added
to the system time.
PTP Packet Structure
The time sync implementation supports both the 1588 V1 and V2 PTP frame formats.
The V1 structure can come only as UDP payload over IPv4 while the V2 can come over
L2 with its Ethertype or as a UDP payload over IPv4 or IPv6.The 802.1AS uses only the
layer 2 V2 format.
1. Write the lower portion of the offset to TIMADJL.
2. Write the high portion of the offset to TIMADJH to the lower 31 bits and the sign to
Offset in Bytes
the most significant bit.
Bits
10
11
12
13
14
15
16
17
18
19
20
21
0
1
2
3
4
5
6
7
8
9
versionPTP
versionNetwork
Subdomain
messageType
Source communication
technology
7 6 5 4 3 2 1 0
V1 Fields
transportSpecific
Reserved
messageLength
SubdomainNumber
Reserved
flags
correctionNs
correctionSubNs
reserved
Source communication technology
Reserved
7 6 5 4 3 2 1 0
V2 Fields
1
messageId
versionPTP
195