WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 299

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
Note:
10.2.2.4
Note:
10.2.2.5
output from the NVM is latched into bit 3 of this register via the internal 62.5 MHz clock
and may be accessed by software via reads of this register. See
details.
Attempts to write to the Flash device when writes are disabled (FWE=01) should not be
attempted. Behavior after such an operation is undefined, and can result in component
and/or system hangs.
EEPROM Read Register - EERD (0x00014; RW)
This register is used by software to cause the 82574 to read individual words in the
EEPROM. To read a word, software writes the address to the Read Address field and
simultaneously writes a 1b to the Start Read field. The 82574L reads the word from the
EEPROM and places it in the Read Data field, setting the Read Done field to 1b.
Software can poll this register, looking for a 1b in the Read Done field, and then using
the value in the Read Data field.
When this register is used to read a word from the EEPROM, that word is not written to
any of the 82574's internal registers even if it is normally a hardware accessed word.
Extended Device Control Register - CTRL_EXT (0x00018; RW)
START
DONE
ADDR
DATA
Reserved
ASDCHK
EE_RST
Reserved
Field
Field
0
1
15:2
31:16
11:0
12
13
14
Bit(s)
Bit(s)
0b
1b
0x0
0x0
0x0
0b
0b
0b
Initial
Initial
Value
Value
1
Start Read
Writing a 1b to this bit causes the 82574 to read a 16-bit word at the
address stored in the ADDR field from the NVM. The result is stored in
the DATA field. This bit is self-clearing
Read Done
Set to 1b when the word read completes. Set to 0b when the read is
in progress. Writes by software are ignored.
Read Address
This field is written by software along with Start Read to indicate the
word address of the word to read.
Read Data
Data returned from the NVM.
Reserved.
ASD (Auto Speed Detection) Check
Initiate an ASD sequence to sense the frequency of the RX_CLK signal
from the PHY. The results are reflected in STATUS.ASDV. This bit is
self-clearing.
EEPROM Reset
Initiates a reset-like event to the EEPROM function. This causes the
EEPROM to be read as if a PCI_RST_N assertion had occurred.
Note: All device functions should be disabled prior to setting this bit.
This bit is self-clearing.
Reserved
Should be set to 0b.
Description
Description
Section 3.3.8
for
299