WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 147

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
7.1.10
Receive interrupts can also be generated for the following events:
Receive Packet Checksum Offloading
The 82574L supports the offloading of three receive checksum calculations: the packet
checksum, the IPv4 header checksum, and the TCP/UDP checksum.
The packet checksum is the one's complement over the receive packet, starting from
the byte indicated by RXCSUM.PCSS (zero corresponds to the first byte of the packet),
after stripping. For packets with VLAN header the packet checksum includes the header
if VLAN striping is not enabled by the CTRL.VME. If VLAN header strip is enabled, the
packet checksum and the starting offset of the packet checksum exclude the VLAN
header due to masking of VLAN header. For example, for an Ethernet II frame
encapsulated as an 802.3ac VLAN packet and CTRL.VME is set and with RXCSUM.PCSS
set to 14, the packet checksum would include the entire encapsulated frame, excluding
the 14-byte Ethernet header (DA, SA, Type/Length) and the 4-byte q-tag. The packet
checksum does not include the Ethernet CRC if the RCTL.SECRC bit is set.
Software must make the required offsetting computation (to back out the bytes that
should not have been included and to include the pseudo-header) prior to comparing
the packet checksum against the TCP checksum stored in the packet.
For supported packet/frame types, the entire checksum calculation can be offloaded to
the 82574. If RXCSUM.IPOFLD is set to 1b, the 82574 calculates the IPv4 checksum
and indicates a pass/fail indication to software via the IPv4 Checksum Error bit
(RDESC.IPE) in the Error field of the receive descriptor. Similarly, if RXCSUM.TUOFLD is
set to 1b, the 82574 calculates the TCP or UDP checksum and indicates a pass/fail
condition to software via the TCP/UDP Checksum Error bit (RDESC.TCPE). These error
bits are valid when the respective status bits indicate the checksum was calculated for
the packet (RDESC.IPCS and RDESC.TCPCS respectively). Similarly, if RFCTL.Ipv6_DIS
and RFCTL.IP6Xsum_DIS are cleared to 0b and RXCSUM.TUOFLD is set to 1b, the
82574 calculates the TCP or UDP checksum for IPv6 packets. It then indicates a pass/
fail condition in the TCP/UDP Checksum Error bit (RDESC.TCPE).
If neither RXCSUM.IPOFLD nor RXCSUM.TUOFLD are set, the Checksum Error bits (IPE
and TCPE) are 0b for all packets.
Supported frame types:
• Receive Descriptor Minimum Threshold (ICR.RXDMT)
• Receiver FIFO Overrun (ICR.RXO)
• Ethernet II
• Ethernet SNAP
— The minimum descriptor threshold helps avoid descriptor under-run by
— FIFO overrun occurs when hardware attempts to write a byte to a full FIFO. An
generating an interrupt when the number of free descriptors becomes equal to
the minimum. It is measured as a fraction of the receive descriptor ring size.
This interrupt would stop and re-initialize the entire active delayed receives
interrupt timers until a new packet is observed.
overrun could indicate that software has not updated the tail pointer(s) to
provide enough descriptors/buffers, or that the PCIe bus is too slow draining
the receive FIFO. Incoming packets that overrun the FIFO are dropped and do
not affect future packet reception. This interrupt would stop and re-initialize the
entire active delayed receives interrupts.
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