WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 295

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
Note:
Note:
Note:
1. These bits are read from the NVM.
This register, as well as the Extended Device Control (CTRL_EXT) register, controls the
major operational modes for the device. While a software write to this register to
control device settings, several bits (such as FD and Speed) might be overridden
depending on other bit settings and the resultant link configuration determined by the
PHY's auto-negotiation resolution. See
link configuration process.
In half-duplex mode, the 82574 transmits carrier extended packets and can receive
both carrier extended packets and packets transmitted with bursting.
When using an internal PHY, the FD (duplex) and Speed configuration of the device is
normally determined from the link configuration process. Software can specifically
override/set these MAC settings via these bits in a forced-link scenario; if so, the values
used to configure the MAC must be consistent with the PHY settings.
Manual link configuration is controlled through the PHY's MII management interface.
The ADVD3WUC bit (Advertise D3Cold Wakeup Capability Enable control) enables the
AUX_PWR pin to determine whether D3Cold support is advertised. If full 1 Gb/s
operation in D3 state is desired but the system's power requirements in this mode
would exceed the D3Cold Wakeup-Enabled specification limit (375 mA at 3.3 V dc), this
bit can be used to prevent the capability from being advertised to the system.
When using the internal PHY, by default the PHY re-negotiates the lowest functional link
speed in D3 and D0u states. The PHYREG 25.2 bit enables this capability to be disabled,
in case full 1 Gb/s speed is desired in these states.
The 82574L internal PHY automatically detects an unplugged LAN cable and reduce
operational power to the minimal amount required to maintain system operation.
Controller operations are not affected, except for the inability to transmit/receive due
to the lost link.
Device Reset (RST) might be used to globally reset the entire component. This register
is provided primarily as a last-ditch software mechanism to recover from an
indeterminate or suspected hung hardware state. Most registers (receive, transmit,
interrupt, statistics, etc.), and state machines are set to their power-on reset values,
approximating the state following a power-on or PCI reset. However, PCIe configuration
registers are not reset, thereby leaving the device mapped into system memory space
and accessible by a software device driver. One internal configuration register, the
Packet Buffer Allocation (PBA) register, also retains its value through a global reset.
To ensure that global device reset has fully completed and that the 82574 responds to
subsequent accesses, designers must wait approximately 1 s after resetting before
attempting to check to see if the bit has cleared or attempting to access (read or write)
any other device register.
Before issuing this reset, software has to insure that Tx and Rx processes are stopped
by following the procedure described in
PHY_RST
Field
31
Bit(s)
0b
Initial
Value
PHY Reset
Controls a hardware-level reset to the internal PHY.
0b = Normal (operational).
1b = Reset to PHY asserted.
Section 3.2.3
Section
3.1.3.10.
for a detailed explanation on the
Description
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