WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 307

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
1. These bits are read from the NVM.
The following mapping is used to specify the LED control source (MODE) for each LED
output:
LED2_MODE
Reserved
LED2_BLINK_
MODE
LED2_IVRT
LED2_BLINK
Reserved
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Field
MODE
19:16
20
21
22
23
31:24
Bit(s)
LINK_10/1000
LINK_100/1000
LINK_UP
FILTER_ACTIVITY
LINK/ACTIVITY
LINK_10
LINK_100
LINK_1000
Reserved
FULL_DUPLEX
COLLISION
ACTIVITY
BUS_SIZE
PAUSED
LED_ON
LED_OFF
Selected Mode
0110b
0b
0b
0b
0b
0x0
Initial
Value
1
1
1
1
LED2 (LINK_100_N) Mode
This field specifies the control source for the LED2 output. An initial
value of 0110b selects LINK_100 indication.
Reserved
Read-only as 0b. Write as 0b for future compatibility.
LED2 (LINK_100_N) Blink Mode
This field needs to be configured with the same value as
GLOBAL_BLINK_MODE, it specifies the blink mode of the LED.
0b = Blink at 200 ms on and 200 ms off.
1b = Blink at 83 ms on and 83 ms off.
LED2 (LINK_100_N) Invert.
LED2 (LINK_100_N) Blink
Reserved
Asserted when either 10 or 1000 Mb/s link is established
and maintained.
Asserted when either 100 or 1000 Mb/s link is
established and maintained.
Asserted when any speed link is established and
maintained.
Asserted when link is established and packets are being
transmitted or received that passed MAC filtering.
Asserted when link is established AND when there is NO
transmit or receive activity.
Asserted when a 10 Mb/s link is established and
maintained.
Asserted when a 100 Mb/s link is established and
maintained.
Asserted when a 1000 Mb/s link is established and
maintained.
Reserved
Asserted when the link is configured for full-duplex
operation.
Asserted when a collision is observed.
Asserted when link is established and packets are being
transmitted or received.
Asserted when the device detects a 1-lane PCIe
connection.
Asserted when the device’s transmitter is flow controlled.
Always asserted.
Always de-asserted.
Description
Source Indication
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