DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 87

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

19-4750; Rev 1; 07/11
G. Field
Name
JBS
PS
PCS
EMIS
RSVD
EMAWS
EMARS
GSR2.
PPTCSL
GSR3.
PPRCSL
GSR4.
PPS
GSR5.
BGS
Addr (A:)
Bit [x:y]
A:0034h
A:0038h
A:003Ch
A:0040h
[31:0] rls-crw-i3
[31:0] rls-crw-i3
[31:0] ros-crw-i2
[31:0] ros-_-i2
[6] ros-_-i1
[5] ros-_-i1
[4] ros-_-i1
[3] ros-_-i1
[2]
[1] ros-_-i1
[0] ros-_-i1
Type
Description
Jitter Buffer Status = “1” indicates one or more Jitter Buffer Status bits are “1”
(G.GSR6). The combination of JBS = 1 and G.GSRIE1.JBIE = 1 forces an
interrupt on INT_N.
Port Status = “1” indicates one or more TDM Per Port Status bits are “1”
(G.GSR4). The combination of PS = 1 and G.GSRIE1.PIE = 1 forces an interrupt
on INT_N.
Packet Classifier Status = “1” indicates one or more Packet Classifier special
event/errors have been detected (PC.SRL) and enabled (PC. SRIE). An interrupt
is generated on INT_N when PCS = 1 and G.GSRIE1.PCIE = 1.
External Memory Interface Status = “1” indicates one or more SDRAM Queue
Errors have been detected (EMI.BMSRL) and enabled (EMI.BMSRIE). An
interrupt is generated on INT_N when EMIS = 1 and G.GSRIE1.EMIIE = 1.
Reserved.
External Memory Access Write Status = “1” indicates one or more TXP CPU
Packet Write Status Latch bits = “1” (EMA.WSRL1) and enabled (EMA.WSRIE1).
The combination of EMAWS = 1 and G.GSRIE1.EMAWIE = 1 forces an interrupt
on INT_N.
External Memory Access Read Status = “1” indicates one or more RXP CPU
Packet Read Status Latch bits = “1” (EMA.RSRL1) and enabled (EMA.RSRIE1).
The combination of EMARS = 1 and G.GSRIE1.EMARIE = 1 forces an interrupt
on INT_N.
Global Status Register 2. Default: 0x00.00.00.00
Per-Port Transmit (RXP) CAS Latched Status = “1” in PPTCSL bit position “x”
(x = 0 to 31) indicates one or more received RXP CAS Codes for Transmit TDM
Port “x” have changed. The combination of any PPTCSL[x] = 1 and its associated
G.GSRIE2.PPTCSIE[x] = 1 will make G.GSR1.PTCS = 1.
Global Status Register 3. Default: 0x00.00.00.00
Per-Port Receive (TXP) CAS Latched Status = “1” in PPRCSL bit position “x” (x
= 0 to 31) indicates one or more CAS Codes received from TDM Port “x” have
changed (TXP direction). The combination of any PPRCSL[x] = 1 and its
associated G.GSRIE3.PPRCSIE[x] = 1 will make G.GSR1.PRCS = 1.
Global Status Register 4. Default: 0x00.00.00.00
Per-Port Latched Status = “1” in PPS bit “x” (x = 0 to 31) indicates one or more
Frame Alignment or Over/underrun errors have been detected at TDM Port “x”
(any “Pn.PTSRL[z] and Pn.PTSRIE[z]” = 1 or any “Pn.PRSRL[z] and
Pn.PTSRIE[z]” = 1; where “Pn” = “Port x” and z = bit 0 or bit 1). This is a latched
status register, which means a 0 to 1 transition on any associated
PTSRL[z]/PRSRL[z] forces a latched PPS=1. The G.GCR.LSBCRE register
selects whether a Read or Write operation to GSR4 clears the register (-crw-;
even if all PTSRL[z]/PRSRL[z] transition back to “0”, a PPS[x] = 1 value will not
clear until GSR4 is cleared by a Read or Write operation). Any PPS[x] = 1 will
force G.GSR1.PS = 1.
Global Status Register 5. Default: 0x00.00.00.00
Bundle Group Status = “1” in BGS bit position “x” (x = 0 to 31) indicates one or
more PW Control Word changes have been detected in Bundle Group “x” (any
B.GxSRL[z] = 1 and B.GxSRIE[z] = 1 for z = 0 to 7). Bundles with a detected
change can be identified from: Bundle # = BGS “x” bit position x 8 + B.GxSRL “z”
bit position. Any BGS[x] = 1 (x = 0 to 31) will force G.GSR1.BS = 1.
DS34S132 DATA SHEET
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