DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet
DS34S132GNA2+
Specifications of DS34S132GNA2+
Related parts for DS34S132GNA2+
DS34S132GNA2+ Summary of contents
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... MEF OAM Broadcast DA ♦ DDR SDRAM Interface ♦ Low-Power 1.8V Core, 3.3V I/O, 2.5V SDRAM 100/1000 MII/ Ethernet PART GMII MAC DS34S132GNA2 DS34S132GNA2+ Clock Adapter +Denotes a lead(Pb)-free/RoHS-compliant package. Clock Inputs & Outputs DS34S132 Features Adaptive Clock Recovery Differential Clock Recovery Absolute and Differential Timestamps “ ...
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TABLE OF CONTENTS 1 Introduction .................................................................................................................................................... 8 2 Acronyms and Glossary ................................................................................................................................. 9 3 Applicable Standards ................................................................................................................................... 10 4 High Level Description ................................................................................................................................. 11 5 Application Examples ................................................................................................................................... 13 6 Block Diagram ............................................................................................................................................. 15 7 Features ...................................................................................................................................................... 16 8 Pin ...
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IP Packets with Unknown IP Protocol (DPS4) ................................................................. 60 9.3.2.3.10 IP Packet with Unknown IP Destination Address (PC.CR6 – PC.CR16 and DPS1) ......... 60 9.3.2.3.11 “CPU Debug RXP PW Bundle” Setting (RXBDS) ............................................................ 61 9.3.2.3.12 PW Bundle with Unknown ...
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MAC Registers (M.) ..................................................................................................................... 129 10.3.13 TXP SW CAS Registers (TXSCn.) ............................................................................................... 138 10.3.14 Xmt (RXP) SW CAS Registers (RXSCn.) ..................................................................................... 139 10.3.15 TDM Port n Registers (Pn 31)........................................................................................ 140 10.3.15.1 Port n Transmit Configuration ...
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LIST OF FIGURES Figure 5-1. TDMoP in a Metropolitan Packet Switched Network ........................................................................... 13 Figure 5-2. TDMoP in Cellular Backhaul ............................................................................................................... 14 Figure 6-1. DS34S132 Functional Block Diagram ................................................................................................. 15 Figure 9-1. S132 Block Diagram .......................................................................................................................... 28 Figure 9-2. RXP/TXP ...
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LIST OF TABLES Table 3-1. Applicable Standards ......................................................................................................................... 10 Table 8-2. Detailed Pin Descriptions .................................................................................................................... 22 Table 9-2. TDM Port TCLKOn Clock Source Selection ......................................................................................... 36 Table 9-3. TDM Port BFD Settings ....................................................................................................................... 38 Table 9-4. CAS Translation using RSIG ...
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Table 10-40. Global Ethernet Packet Classification (PC.) Settings ...................................................................... 150 Table 10-41. Valid UDP BID Location and UDP Protocol Type Settings.............................................................. 151 Table 10-42. Bundle and OAM Bundle Control Registers (B.) ............................................................................. 151 Table 10-43. SAT Bundle Settings ..................................................................................................................... 152 ...
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INTRODUCTION The public network is in transition from a TDM Switched Network to a Packet Switched Network. A number of Pseudowire (PW) packet protocols have been standardized to enable legacy TDM services (e.g. TDM voice, TDM Leased-line and HDLC ...
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ACRONYMS AND GLOSSARY • # – Number • ACR – Adaptive Clock Recovery • AT – Absolute Timestamps • ATM – Asynchronous Transfer Mode BERT – Bit Error Rate Test • • BGA – Ball Grid Array • BITS ...
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APPLICABLE STANDARDS Table 3-1. Applicable Standards SPECIFICATION ANSI Digital Hierarchy—Electrical Interfaces, 1993 T1.102 Digital Hierarchy—Formats Specification, 1995 T1.107 Network and Customer Installation Interfaces—DS1 Electrical Interface, 1999 T1.403 ETSI ISDN Primary Rate User Network Interface (UNI); Part 1: Layer 1 ...
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HIGH LEVEL DESCRIPTION To implement a PW (tunnel) across a PSN requires a PW termination point at each end of the PW (tunnel). Each terminating point provides the PW encapsulation functions that are required to enter the PSN (for ...
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The DS34S132 uses an external DDR SDRAM device to buffer data. The large memory supplies sufficient buffer space to support a 256 ms PDV for each of the 256 PW/Bundles and to enable packet re-ordering for packets that are received ...
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APPLICATION EXAMPLES In Figure 5-1, TDMoP devices are used in gateway nodes to transport TDM services through a metropolitan PSN. The Maxim TDMoP family of devices offers a range of density solutions so that lower density solutions like the ...
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Figure 5-2. TDMoP in Cellular Backhaul Other Possible Applications Using a Packet Backplane for Multiservice Concentrators Communications platforms with all/any of the above-mentioned capabilities can replace obsolete, low bandwidth TDM buses with low cost, high bandwidth Ethernet buses. The DS34S132 ...
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BLOCK DIAGRAM Figure 6-1. DS34S132 Functional Block Diagram LIUCLK TCLKO[31:0] EXTCLK[1:0] TDM TSYNC[31:0] Port TDM & TDAT[31:0] Port TSA & TSIG[31:0] 1 TSA 32 RCLK[31:0] TDM Port RSYNC[31:0] TDM & RDAT[31:0] Port TSA & RSIG[31:0] 1 TSA 32 JTAG ...
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FEATURES TDM Port Features • TDM Ports • 32 TDM Ports, each with independently configured Framing Format • T1/E1 Structured (with T1/E1 Framing) • T1-SF, T1-ESF and E1 CAS Multi-frame formats • With and Without CAS Signaling CAS embedded ...
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Ethernet Port Features • Ethernet MAC Interface • 100/1000 Mb/s Operation using MII/GMII Interface • 2 programmable receive Ethernet Destination Addresses • Mixed Ethernet II (DIX) and IEEE 802.2 LLC/SNAP formats • Mixed data streams with ...
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Any Nx64 Kb/s bit rate from a single TDM Port • With or without CAS Signaling • HDLC PW/Bundles (e.g. SS7 Signaling) • Unstructured PW Payload: E1, T1 and slower TDM bit rate (≤ 2.048 Mb/s) ...
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TDM Port Timeslot Loopback (from Receive to Transmit TDM Port Timeslot using RCLK) • TDM Port and/or Ethernet Port BERT Testing • Half Channel (one-way) or Full Channel (round-trip) Testing • Flexible PRBS, QRBS or Fixed Pattern Testing • ...
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PIN DESCRIPTIONS 8.1 Short Pin Descriptions Table 8-1. DS34S132 Short Pin Descriptions * Name Type TDM Port through 31 Ports TCLKOn Oz TSYNCn IO TDATn Oz TSIGn Oz RCLKn I RSYNCn IO RDATn I RSIGn I ...
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Name Type SDLDQS Oz SDUDQS Oz Clocks, Resets , JTAG & Miscellaneous CMNCLK I EXTCLK[1:0] I SYSCLK I LIUCLK Oz REFCLK I DDRCLK I ETHCLK I EXTINT I EPHYRST_N Oz RST_N I JTCLK I JTMS Ipu JTDI Ipu JTDO ...
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Detailed Pin Descriptions Table 8-2. Detailed Pin Descriptions Pin Name Type Pin Description TDM Port through 31 Ports Transmit Clock Output. TCLKOn is derived from the clock recovery engine or from TCLKOn Oz RCLKn when in ...
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Pin Name Type Pin Description Receive Data 0 through 7(GMII Mode – RXD[0:7]). Eight bits of received data, RXD[7:0] I sampled synchronously with the rising edge of RXCLK. For every clock cycle, the PHY transfers 8 bits to the device. ...
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Pin Name Type Pin Description Processor Read/Write Control. PRWCTRL PRW is high for a write, low for a read (PQ II Pro mode PRW is low for a write, high for a read (PQ I ...
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Pin Name Type Pin Description Clocks, Resets , JTAG & Miscellaneous Common Clock. This clock is used for Differential Clock Recovery. Common clock CMNCLK I has multiple of 8 kHz and in the range of 8 kHz ...
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Pin Name Type Pin Description Manufacturing Test Output, Must be left unconnected (floating). SMTO O Power Supply Signals VDD33. Connect to 3.3 Volt Power Supply VDD33 pwr VDD18 pwr VDD18. Connect to 1.8 Volt Power Supply VSS pwr VSS. Ground ...
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FUNCTIONAL DESCRIPTION This section provides a high level, functional view of the S132. Because of the high level of integration and complexity that has been included in the S132 necessary to first explain the terminology and conventions ...
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The term “frame” is also used to mean a “125 us TDM time period” but then can be understood to use this meaning from the TDM context of the surrounding text. The term “HDLC” ...
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Connection Types The following subsections describe the different connection types in more detail. 9.1.1 SAT/CES Payload Connections The S132 can support up to 256 SAT/CES Payload Connections spread across 32 TDM Ports. Each SAT/CES Payload Connection carries constant bit ...
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Each HDLC Bundle can be configured to support any number of DS0s up to the entire TDM Port line rate. In the RXP direction the PW Header is stripped off and a Buffer is used to store the complete packet ...
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The most generalized TDMoP PW application recovers TDM timing from a TDMoP PW packet stream. However, for some applications the timing/rate of the TDMoP PW payload data is synchronized to a distributed, common clock reference at both ends of the ...
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TDM Port Functions The S132 includes 32 TDM Ports. Each TDM Port can be used to support a T1 any slower TDM data stream. Each TDM Port uses a serial clock and data interface. The high level ...
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In general, the DCR technique provides better clock recovery performance than the ACR technique (when compared using an equal quality synclk reference input for both techniques). For DCR applications the PW standards assume both ends of the PW use the ...
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Sequence Number. Both Timestamp types provide a measure of time, one referenced to a common clock, the other referenced to the receive TDM Port line rate. In the TXP direction the S132 supports all 3 techniques. The ACR ...
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TDM Port - One Clock and Two Clock Modes Each TDM Port can be independently programmed to support “One Clock” or “Two Clock” operation. In the “One Clock” mode, the transmit and receive directions are both timed relative to ...
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Figure 9-11. Logic Detail for a Single TDM Port Interface EXTCLK0 EXTCLK1 TCLKOn TCE TIOE TDATn TSIGn TDS TSYNCn RDATn RSIGn RDS RSYNCn RCLKn 9.2.2.1 TDM Port Transmit Interface The T1/E1 Transmit interface is controlled using the TIOE: Enable/disable the ...
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TDM Port Receive Interface The T1/E1 Receive interface is controlled using the functions (more of the PRCR1 functions are described in the sub-sections that follow): RSTS: Select the receive framing to be synchronized to RDS: Select RSYNCn RIES: Select ...
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Fragment byte depth (e.g. 24 bytes for T1). are used by each Staging Buffer (4 Fragments will store data for 125 us = 500 us period). BPF should be set to the number of bytes exchanged ...
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Figure 9-13. TSA Block Environment DS34S132 TXP Cond Data Rcv TDM Port Bundle Loopback Xmt TDM Port Xmt CAS Monitor One Timeslot Assigner circuit is provided for each TDM Port and in each direction so that any combination of timeslots ...
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Xmt SW CAS will only be sent when the Jitter Buffer is empty). These two functions are programmed on a per-Bundle basis. The Xmt SW CAS codes are programmed using (programmed on a per-Timeslot basis). In the TXP direction, ...
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ESF formats. For the T1 SF format this means that two successive 2-bit CAS Codes from 2 consecutive SF frames are stored. For T1 ESF and E1, the 4-bit ABCD CAS-codes received at a T1/E1 Port are stored and forwarded ...
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Table 9-5. CAS Translation using RDAT and TDAT TXP Direction TDM Port RDAT SCTXDFSE to PRCR1.MFS Format Frm 1-12 Frm 13-24 ESF ESF ...
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Bundle is equivalent to enabling a “Connection” for that Engine (e.g. enabling SAT/CES Engine = enable SAT/CES Connection). B.BCDR1.RXBDS forward the packets for a Bundle to the CPU (for debug; CPU Debug RXP PW Bundle discard the ...
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Each HDLC Engine can be programmed to use MSbit or LSbit first transmission (BCDR1.SCSNRE). This function does not specify which bits of the Timeslot are used (previous paragraphs), but instead specifies whether the MSbit or LSbit of each HDLC coded ...
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For RXP Bundles, the S132 monitors the received Control Word L-bit field. If the RXP Bundle is programmed with B.BCDR1.SCSCFPD = 1 (verify packet size) and the received L-bit = “0” (“PW payload is valid”), the S132 discards the packet ...
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The delay of data at the input of the Jitter Buffer is caused by fixed and PDV (variable) delay parameters according to the equation below. Maximum Jitter Buffer Input Delay = PCT + fixed transmission and circuit processing delay + ...
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TDM Line. Table 9-7. Maximum S132 Ethernet Media PDV Maximum Number Packet Size for 100 Mb/s Interface of Bundles 64 Bytes 32 Bundles ...
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The PDVT setting specifies how much data must be stored by the Jitter Buffer before “play-out” (FIFO read) begins. After “play-out” begins the Jitter Buffer will continue to supply data until the Jitter Buffer is empty. If the Jitter Buffer ...
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PCT”. You could say that this approach assumes the PDV = 0 for the first packet. The maximum number of ...
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The Jitter Buffer Maximum Fill Level generally determines the maximum delay. Although the fill level will initially stabilize at a level just high enough to support the Total PDV, when anomalies occur (e.g. temporary line failures and RXP PW protection ...
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Figure 9-17. T1/E1 Port Line Loopback and TDM Port Timeslot Loopback Diagram T1/E1 Framer/LIU The TDM Bundle Loopback is enabled using loopback takes received RXP packet data and re-transmits that data in TXP packets. To work properly, when this loopback ...
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The Half Channel (one-way) Test requires an equivalent BERT Tester at the far end (on the left side of the diagram). The S132 BERT Pattern Generator sends a BERT Pattern to the S132 Transmit TDM Port. The far end uses ...
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Packet Processing Functions The S132 includes one Ethernet Port to receive and transmit Ethernet packets. The high level functions include: • 100 Mbps MII or 1000 Mbps GMII Interface • Ethernet II and IEEE 802.2 LLC/SNAP formats • 0, ...
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In some cases time (as long as the RXCLK output from the Phy is a constant, non-gapped 125 MHz signal). M.NET_CONTROL.TXP_HALT, START_TXP, data at the Ethernet MAC/Port. The MAC must be programmed to operate in the Full-duplex ...
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Figure 9-22. Ethernet Port BERT Diagram S132 T1/E1 Framer/ RXP Packet Decap BERT LIU Monitor TXP Packet Encap BERT X Generator The Full Channel (Roundtrip) Test requires a loopback at the far end (on the right side of the diagram). ...
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The DB.BCR register is used to program the Packet BERT Monitor for New Test Pattern Load (RNPL), Test Pattern Inversion (RPIC), Manual Resynchronization (MPR) and Pattern Resynchronization Disable (APRD). The DB.BSR, DB.BSRL, DB.BSRIE, DB.RBECR, The Packet BERT Generator can be ...
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PC.CR1.RXPDSD packet is received that includes an Ethernet Type field that is equal version that is not enabled, the packet is discarded. According to the enabled IP version(s), the S132 can recognize ...
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The S132 includes several BID/OAM BID settings and tests for UDP applications that are not used by the non-UDP applications. These are explained in the “UDP Settings” section. For non-UDP applications, the “UDP Settings” section can be skipped/ignored. 9.3.2.2.1 UDP ...
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Table 9-9. Malformed PW Header Handling (not including the UDP specific settings) Test Description Wrong Payload Size RTP Header existence Control Word Header existence Wrong # L2TPv3 Cookies or MPLS Labels The first nibble of the Control Word of a ...
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CPU conditions” are described together in one section (e.g. OAM BIDs, In-band VCCV, “CPU Debug RXP PW Bundle” and error condition Discard Switches). 9.3.2.3.1 Packets with Broadcast Ethernet DA When an Ethernet packet ...
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Debug RXP PW Bundle” Setting (RXBDS) PW Bundles (not including OAM Bundles) are normally used for SAT, CES, HDLC or PW-Timing Connections, but can be programmed to instead send packets to the CPU for debug. When the CPU ...
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TXP SAT/CES/HDLC/Clock Only PW Packet Generation A TXP Header Descriptor is programmed for each activated SAT, CES, HDLC and Clock Only Bundle (up to 256). The TXP Header Descriptors are retrieved from memory as they are needed for each ...
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TXP SAT/CES/Clock Only Packets can optionally include an RTP Timestamp using the RTP Exists field in the TXP Header Descriptor Header Control (RTP is not commonly used with HDLC Bundles). A TXP HDLC packet is generated for each HDLC packet ...
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CPU Packet. The format of the packet and Header Descriptor are provided in through Table 9-14. Figure 9-26. Stored RXP CPU Packet ...
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Table 9-13. RXP CPU Header Descriptor – 2 Field Bit [x:y] Description Reserved. RSVD [31:30] RXIPV6 [29] RXP IPv6 packet IPv6 Header not IPv6. RXP IPv4 packet IPv4 Header not IPv4. RXIPV4 ...
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The CPU process of Reading the RXP CPU packets can be polling based using the interrupt driven using the EMA.RSRL1.RFRSL bits. When the CPU detects that a packet is waiting in the RXP CPU FIFO, the CPU must specify the ...
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When TXOTSE is enabled, TXOTSO identifies the OAM Timestamp Dword position in the packet. The CPU must make the initial OAM Timestamp value 0x0000 in the packet stored in the TXP CPU FIFO. The S132 overwrites that position with the ...
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The EMA.WSR1, EMA.WSR2, EMA.WSRL1 the TXP CPU FIFO and the SDRAM TXP CPU Queue. 9.5 Clock Recovery Functions The S132 includes a DSP to implement its Clock Recovery functions. The Clock Recovery functions include the RXP and TXP PW-Timing functions. ...
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SDRAM Interface The S132 has been designed to work with DDR-SDRAM devices that are compatible with the JEDEC JESD79C standard and that support 2-2-2 timing with a clock rate of at least 125 MHz. device sizes that can be ...
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Figure 9-29. MPC870 32-bit Bus Interface VDD33 MPC870 LCLK LCSn LBCTL LGTA IRQn LA[12] LA[13] LA[14] LA[15] LA[16] LA[17] LA[18] LA[19] LA[20] LA[21] LA[22] LA[23] LA[24] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] ...
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Figure 9-30. MPC8313, Non-multiplexed Bus Interface VDD33 MPC8313 VSS LCLK LCSn LBCTL LGTA IRQn LA[12] LA[13] LA[14] LA[15] LA[16] LA[17] LA[18] LA[19] LA[20] LA[21] LA[22] LA[23] LA[24] Not used LAD[0] LAD[1] LAD[2] LAD[3] LAD[4] LAD[5] LAD[6] LAD[7] LAD[8] LAD[9] LAD[10] ...
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G.GCR1.IIM. each other. Table 9-18. Interrupt Hierarchy Monitor Function Level 3 Interrupt Condition Registers G.GSR1 Interrupts Status Latched Status Ethernet Port BERT EB.BSR EB.BSRL TDM Port BERT DB.BSR DB.BSRL TXP packet CAS NA ...
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Figure 9-32. Interrupt Hierarchy Diagram G.GSR1 Level 3 Status[0:0] Monitor Function "A" [0,0] Latch Status[0:y] Monitor Function "A" [0,y] Latch Monitor Function "A" [0,0] Interrupt En Monitor Function "A" [0,y] Interrupt En Status[x:0] Monitor Function "A" [x,0] Latch Status[x:y] Monitor ...
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DEVICE REGISTERS 10.1 Register Block Address Ranges Table 10-1. Register Block Address Ranges Registers Global Registers Global Configuration Registers (G.) Global Status Registers (G.) Global Status Register Interrupt Enables (G.) Individual Bundle and Jitter Buffer Registers Global Bundle Reset ...
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Register Address Reference List Table 10-2. Register Address Reference List Register Name Addr (hex) Global Configuration Registers (G.) IDR. GCR GRCR CCR ECCR1 ECCR2 TCCR1 TCCR2 Global Status Registers (G.) GSR1 GSR2 GSR3 GSR4 GSR5 GSR6 TPISR1 TPISR2 TPISR3 ...
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Register Name Addr (hex) BDSR7 BDSR8 BDSR9 Bundle Group Status Latch Registers (B.) G0SRL G1SRL G2SRL G3SRL G4SRL G5SRL G6SRL G7SRL G8SRL G9SRL G10SRL G11SRL G12SRL G13SRL G14SRL G15SRL G16SRL G17SRL G18SRL G19SRL G20SRL G21SRL G22SRL G23SRL G24SRL G25SRL G26SRL ...
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Register Name Addr (hex) G18SRIE G19SRIE G20SRIE G21SRIE G22SRIE G23SRIE G24SRIE G25SRIE G26SRIE G27SRIE G28SRIE G29SRIE G30SRIE G31SRIE Jitter Buffer Status Registers (JB.) G0SRL G1SRL G2SRL G3SRL G4SRL G5SRL G6SRL G7SRL G8SRL G9SRL G10SRL G11SRL G12SRL G13SRL G14SRL G15SRL G16SRL ...
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Register Name Addr (hex) G7SRIE G8SRIE G9SRIE G10SRIE G11SRIE G12SRIE G13SRIE G14SRIE G15SRIE G16SRIE G17SRIE G18SRIE G19SRIE G20SRIE G21SRIE G22SRIE G23SRIE G24SRIE G25SRIE G26SRIE G27SRIE G28SRIE G29SRIE G30SRIE G31SRIE Packet Classifier Configuration Registers (PC.) CR1 CR2 CR3 CR4 CR5 CR6 ...
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Register Name Addr (hex) FOCR External Memory Interface Configuration Registers (EMI.) BMCR1 BMCR2 BMCR3 DCR1 DCR2 DCR3 External Memory Interface Status Registers (EMI.) BMSRL External Memory Interface Status Interrupt Enable Registers (EMI.) BMSRIE External Memory Interface Test Status Registers (EMI.) ...
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Register Name Addr (hex) TSTCR Miscellaneous Diagnostic Registers (MD.) DCR EBCR DBCR MBSR1 MBSR2 MBSR3 MBSR4 MBSR5 Test Registers (TST.) GTR1 BTCR1 BTCR2 BTCR3 BTCR4 BTCR5 BTCR6 CRJBT BTSR1 BTSR2 BTSR3 BTSR4 BTSR5 BTSR6 CTCR1 CTCR2 CTCR3 CTCR4 EDTCR EDTSR1 ...
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Register Name Addr (hex) HASH_BOT HASH_TOP LADDR1_BOT LADDR1_TOP LADDR2_BOT LADDR2_TOP LADDR3_BOT LADDR3_TOP LADDR4_BOT LADDR4_TOP ID_CHECK1 ID_CHECK2 ID_CHECK3 ID_CHECK4 RSVD IPG_STRETCH MOD_ID OCT_TX_BOT OCT_TX_TOP STATS_FRAMES_TX BROADCAST_TX MULTICAST_TX STATS_PAUSE_TX FRAME64_TX FRAME65_TX FRAME128_TX FRAME256_TX FRAME512_TX FRAME1024_TX FRAME1519_TX STATS_TX_URUN STATS_SINGLE_COL STATS_MULTI_COL STATS_LATE_COL STATS_DEF_TX STATS_CRS_ERRORS ...
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Register Name Addr (hex) STATS_ALIGN_ERRORS STATS_RX_RES_ERR STATS_RX_ORUN IP_HDR_CHK TCP_CHK UDP_CHK RSVD REG_TOP Port n TXP SW CAS Registers (TXSCn 31) CR1 1000 + n*0010 CR2 1004 + n*0010 CR3 1008 + n*0010 CR4 100C + n*0010 ...
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Register Definitions In the sub-sections that follow each register definition includes a Register Type definition with 3 Type Categories: Signal Type, Clear Type and Misc Type. The Type definition uses the form “a-b-c” where a = Signal Type, b ...
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G. Field Addr (A:) Name Bit [x:y] Type EC25 [27] rwc-_-_ ECDC [26] rwc-_-_ IIM [25] rwc-_-_ RDPC [24] rwc-_-_ JLPC [23] rwc-_-_ IPSE [22] rwc-_-_ JBMD [21:20] rwc-_-_ GRCSS [19:15] rwc-_-_ GMMS [14:12] rwc-_-_ CCOR [11] rwc-_-_ RXHMFIS [10:8] ...
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G. Field Addr (A:) Name Bit [x:y] Type MBCDE [3:2] rwc-_-_ FBCDE [1:0] rwc-_-_ GRCR. A:0008h RSVD [31:11] CCRSTDP [10] DRSTDP [9] SCRSTDP [8] MRSTDP [7] EMARSTDP [6] TERSTDP [5] TDRSTDP [4] TPIRSTDP [3] [2] RPIRSTDP RSTDP [1] rwc-_-_ RST ...
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G. Field Addr (A:) Name Bit [x:y] Type ECCR2. A:0014h ECOE [31:24] rwc-_-_ ECOF [23:16] rwc-_-_ ECOG [15:8] rwc-_-_ ECOH [7:0] rwc-_-_ TCCR1. A:0018h TCOA [31:24] rwc-_-_ TCOB [23:16] rwc-_-_ TCOC [15:8] rwc-_-_ TCOD [7:0] rwc-_-_ TCCR2. A:001Ch ETCOE [31:24] ...
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G. Field Addr (A:) Name Bit [x:y] Type JBS [6] ros-_-i1 PS [5] ros-_-i1 PCS [4] ros-_-i1 EMIS [3] ros-_-i1 RSVD [2] EMAWS [1] ros-_-i1 EMARS [0] ros-_-i1 GSR2. A:0034h PPTCSL [31:0] rls-crw-i3 GSR3. A:0038h PPRCSL [31:0] rls-crw-i3 GSR4. A:003Ch ...
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G. Field Addr (A:) Name Bit [x:y] Type GSR6. A:0044h JBGS [31:0] ros-_-i2 TPISR1. A:0048h RSVD [31:11] TXHPQL [10:0] ros-_-_ TPISR2. A:004Ch RSVD [31:11] TXLPQL [10:0] ros-_-_ TPISR3. A:0050h RSVD [31:10] TXCQL [9:0] ros-_-_ TPISRL. A:0054h RSVD [31:3] HPQOSL [2] ...
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G. Field Addr (A:) Name Bit [x:y] Type JBUIE [6] rwc-_-i1 PIE [5] rwc-_-i1 PCIE [4] rwc-_-i1 EMIIE [3] rwc-_-i1 RSVD [2] EMAWIE [1] rwc-_-i1 EMARIE [0] rwc-_-i1 GSRIE2. A:0064h PPTCIE [31:0] rwc-_-i3 GSRIE3. A:0068h PPRCIE [31:0] rwc-_-i3 10.3.2 Bundle ...
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B. Field Addr (A:) Name Bit [x:y] Type RXBRS [1] ros-_-_ TXBRS [0] ros-_-_ 10.3.2.2 Bundle Data Control Registers (B.) Table 10-7. Bundle Data Control Registers (B.) B. Field Addr (A:) Name Bit [x:y] Type BACR. A:0094h RSVD [31:13] OBS ...
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B. Field Addr (A:) Name Bit [x:y] Type BDSCR. A:00A0h RSVD [31:11] DSRE [10] rwc-_-_ RSVD [9:8] rwc-_-_ DSBS [7:0] rwc-_-_ 10.3.2.3 Bundle Data Registers (B.) Table 10-8. Bundle Data Registers (B.) B. Field Addr (A:) Name Bit [x:y] Type ...
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B. Field Addr (A:) Name Bit [x:y] Type PMS [20:10] rwd-_-_ SCSCFP [9] rwd-_-_ D SCSNRE [8] rwd-_-_ SCRXBC [7] rwd-_-_ SS SCTXBC [6] rwd-_-_ SS RSNS [5] rwd-_-_ SCTXCE [4] rwd-_-_ 19-4750; Rev 1; 07/11 Description Payload Size. The ...
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B. Field Addr (A:) Name Bit [x:y] Type SCTXDF [3] rwd-_-_ SE SCTXCO [2:0] rwd-_-_ S BCDR2. A:00B0h ATSS [31:0] rwd-_-_ BCDR3. A:00B4h RSVD [31:5] TXPMS [4:3] rwd-_-_ TXBTS [2:1] rwd-_-_ TXBPS [0] rwd-_-_ BCDR4. A:00B8h RSVD [31:22] RXRE [21] ...
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B. Field Addr (A:) Name Bit [x:y] Type RXCWE [20] rwd-_-_ RXHTS [19:18] rwd-_-_ RXBTS [17:16] rwd-_-_ RXLCS [15:14] rwd-_-_ RXUBIDL [13] rwd-_-_ S SCLVI [12] rwd-_-_ RXCOS [11:9] rwd-_-_ RXOICW [8] rwd-_-_ E RXBDS [7:6] rwd-_-_ 19-4750; Rev 1; ...
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B. Field Addr (A:) Name Bit [x:y] Type PNS [5:1] rwd-_-_ PCRE [0] rwd-_-_ BCDR5. A:00BCh RSVD [31:25] PDVT [24:10] rwd-_-_ MJBS [9:0] rwd-_-_ BESR1. A:00C0h PRHASL [31] rld-cor-_ RSVD [30:20] PRHEFC [19:0] rld-cnr-nc BESR2. A:00C4h GPTXC [31:0] rld-cnr-nc BESR3. ...
Page 96
B. Field Addr (A:) Name Bit [x:y] Type BDSR2. A:00D4h RSVD [31:20] JBEC [19:0] rld-cnr-nc BDSR3. A:00D8h RSVD [31] JBLL [30:16] rld-cor-_ RSVD [15] JBHL [14:0] rld-cor-_ BDSR4. A:00DCh GPRXC [31:0] rld-cnr-nc BDSR5. A:00E0h SCJPC [31:0] rld-cnr-nc BDSR6. A:00E4h RSVD ...
Page 97
B. Field Addr (A:) Name Bit [x:y] Type PLESL [22] rld-cor-_ SCJBEP [21] rld-cor-_ DSL JBCL [20:6] rod-_-_ LBD [5] rod-_-_ RBD [4] rod-_-_ DMD [3:2] rod-_-_ FBD [1:0] rod-_-_ BDSR8. A:00ECh RSVD [31:20] SCMPC [19:0] rld-cor-_ BDSR9. A:00F0h RSVD ...
Page 98
B. Field Addr (A:) Name Bit [x:y] Type G1SRL. A:0104h RSVD [31:8] CWCDSL [7:0] rls-cor-i3 [15:8] G2SRL. A:0108h RSVD [31:8] CWCDSL [7:0] rls-cor-i3 [23:16] G3SRL. A:010Ch RSVD [31:8] CWCDSL [7:0] rls-cor-i3 [31:24] G4SRL. A:0110h RSVD [31:8] CWCDSL [7:0] rls-cor-i3 [39:32] ...
Page 99
B. Field Addr (A:) Name Bit [x:y] Type G12SRL. A:0130h RSVD [31:8] CWCDSL [7:0] rls-cor-i3 [103:96] G13SRL. A:0134h RSVD [31:8] CWCDSL [7:0] rls-cor-i3 [111:104] G14SRL. A:0138h RSVD [31:8] CWCDSL [7:0] rls-cor-i3 [119:112] G15SRL. A:013Ch RSVD [31:8] CWCDSL [7:0] rls-cor-i3 [127:120] ...
Page 100
B. Field Addr (A:) Name Bit [x:y] Type G23SRL. A:015Ch RSVD [31:8] CWCDSL [7:0] rls-cor-i3 [191:184] G24SRL. A:0160h RSVD [31:8] CWCDSL [7:0] rls-cor-i3 [199:192] G25SRL. A:0164h RSVD [31:8] CWCDSL [7:0] rls-cor-i3 [207:200] G26SRL. A:0168h RSVD [31:8] CWCDSL [7:0] rls-cor-i3 [215:208] ...
Page 101
B. Field Addr (A:) Name Bit [x:y] Type CWCDIE [7:0] rwc-_-i3 [7:0] G1SRIE. A:0184h RSVD [31:8] CWCDIE [7:0] rwc-_-i3 [15:8] G2SRIE. A:0188h RSVD [31:8] CWCDIE [7:0] rwc-_-i3 [23:16] G3SRIE. A:018Ch RSVD [31:8] CWCDIE [7:0] rwc-_-i3 [31:24] G4SRIE. A:0190h RSVD [31:8] ...
Page 102
B. Field Addr (A:) Name Bit [x:y] Type CWCDIE [7:0] rwc-_-i3 [95:88] G12SRIE. A:01B0h RSVD [31:8] CWCDIE [7:0] rwc-_-i3 [103:96] G13SRIE. A:01B4h RSVD [31:8] CWCDIE [7:0] rwc-_-i3 [111:104] G14SRIE. A:01B8h RSVD [31:8] CWCDIE [7:0] rwc-_-i3 [119:112] G15SRIE. A:01BCh RSVD [31:8] ...
Page 103
B. Field Addr (A:) Name Bit [x:y] Type CWCDIE [7:0] rwc-_-i3 [183:176] G23SRIE. A:01DCh RSVD [31:8] CWCDIE [7:0] rwc-_-i3 [191:184] G24SRIE. A:01E0h RSVD [31:8] CWCDIE [7:0] rwc-_-i3 [199:192] G25SRIE. A:01E4h RSVD [31:8] CWCDIE [7:0] rwc-_-i3 [207:200] G26SRIE. A:01E8h RSVD [31:8] ...
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Jitter Buffer Registers (JB.) 10.3.3.1 Jitter Buffer Status Registers (JB.) Table 10-11. Jitter Buffer Status Registers (JB.) JB. Field Addr (A:) Name Bit [x:y] Type G0SRL. A:0200h RSVD [31:8] JBU [7:0] [7:0] rls-cor-i3 G1SRL. A:0204h RSVD [31:8] JBU [7:0] ...
Page 105
JB. Field Addr (A:) Name Bit [x:y] Type G10SRL. A:0228h RSVD [31:8] JBU [7:0] rls-cor-i3 [87:80] G11SRL. A:022Ch RSVD [31:8] JBU [7:0] rls-cor-i3 [95:88] G12SRL. A:0230h RSVD [31:8] JBU [7:0] rls-cor-i3 [103:96] G13SRL. A:0234h RSVD [31:8] JBU [7:0] rls-cor-i3 [111:104] ...
Page 106
JB. Field Addr (A:) Name Bit [x:y] Type G21SRL. A:0254h RSVD [31:8] JBU [7:0] rls-cor-i3 [175:168] G22SRL. A:0258h RSVD [31:8] JBU [7:0] rls-cor-i3 [183:176] G23SRL. A:025Ch RSVD [31:8] JBU [7:0] rls-cor-i3 [191:184] G24SRL. A:0260h RSVD [31:8] JBU [7:0] rls-cor-i3 [199:192] ...
Page 107
Jitter Buffer Status Register Interrupt Enables (JB.) Table 10-12. Jitter Buffer Status Register Interrupt Enables (JB.) JB. Field Addr (A:) Name Bit [x:y] Type G0SRIE. A:0280h RSVD [31:8] JBUIE [7:0] rwc-_-i3 [7:0] G1SRIE. A:0284h RSVD [31:8] JBUIE [7:0] rwc-_-i3 ...
Page 108
JB. Field Addr (A:) Name Bit [x:y] Type G10SRIE. A:02A8h RSVD [31:8] JBUIE [7:0] rwc-_-i3 [87:80] G11SRIE. A:02ACh RSVD [31:8] JBUIE [7:0] rwc-_-i3 [95:88] G12SRIE. A:02B0h RSVD [31:8] JBUIE [7:0] rwc-_-i3 [103:96] G13SRIE. A:02B4h RSVD [31:8] JBUIE [7:0] rwc-_-i3 [111:104] ...
Page 109
JB. Field Addr (A:) Name Bit [x:y] Type G21SRIE. A:02D4h RSVD [31:8] JBUIE [7:0] rwc-_-i3 [175:168] G22SRIE. A:02D8h RSVD [31:8] JBUIE [7:0] rwc-_-i3 [183:176] G23SRIE. A:02DCh RSVD [31:8] JBUIE [7:0] rwc-_-i3 [191:184] G24SRIE. A:02E0h RSVD [31:8] JBUIE [7:0] rwc-_-i3 [199:192] ...
Page 110
Packet Classifier Registers (PC.) 10.3.4.1 Packet Classifier Configuration Registers (PC.) Table 10-13. Packet Classifier Configuration Registers (PC.) PC. Field Addr (A:) Name Bit [x:y] Type CR1. A:0300h DPDE [31:30] rwc-_-_ RSVD [29:26] DPS10 [25] rwc-_-_ DPS9 [24] rwc-_-_ DPS8 ...
Page 111
PC. Field Addr (A:) Name Bit [x:y] Type DICPE [14] rwc-_-_ DUCPE [13] rwc-_-_ DPLME [12] rwc-_-_ DBTP [11] rwc-_-_ DBCP [10] rwc-_-_ RXPIVS [9] rwc-_-_ RXPDSD [8] rwc-_-_ UPVCE [7] rwc-_-_ UBIDLCE [6] rwc-_-_ UBIDLS [5:4] rwc-_-_ UICECS [3:2] ...
Page 112
PC. Field Addr (A:) Name Bit [x:y] Type CR2. A:0304h UPVC1 [31:16] rwc-_-_ UPVC2 [15:0] rwc-_-_ CR3. A:0308h VOTPID [31:16] rwc-_-_ VITPID [15:0] rwc-_-_ CR4. A:030Ch MET [31:16] rwc-_-_ MOET [15:0] rwc-_-_ CR5. A:0310h VOM [31:16] rwc-_-_ VOV [15:0] rwc-_-_ ...
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PC. Field Addr (A:) Name Bit [x:y] Type CR14. A:0334h IV6A2B [31:0] rwc-_-_ CR15. A:0338h IV6A2C [31:0] rwc-_-_ CR16. A:033Ch IV6A2D [31:0] rwc-_-_ CR17. A:0340h MA1B [31:0] rwc-_-_ CR18. A:0344h MA1A [31:16] rwc-_-_ MA2A [15:0] rwc-_-_ CR19. A:0348h MA2B [31:0] ...
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PC. Field Addr (A:) Name Bit [x:y] Type UPVCSL [6] rls-crw-i3 UBIDLCS [5] rls-crw-i3 L BIDMSL [4] rls-crw-i3 RXPFOSL [3] rls-crw-i3 RXPMES [2] rls-crw-i3 L ICPESL [1] rls-crw-i3 UCPESL [0] rls-crw-i3 10.3.4.3 Packet Classifier Status Register Interrupt Enables (PC.) Table ...
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Packet Classifier Counter Registers (PC.) Table 10-16. Packet Classifier Counter Registers (PC.) PC. Field Addr (A:) Name Bit [x:y] Type CPCR. A:0370h CPC [31:0] rcs-cor-nc PCECR. A:0374h RSVD [31:16] UICPEC [15:0] rcs-cor-nc SPCR. A:0378h SPC [31:0] FOCR. A:037Ch RSVD ...
Page 116
EMI. Field Addr (A:) Name Bit [x:y] Type DCR2. A:0394h RSVD [31:19] TRFC [18:14] rwc-_-_ DCL [13:11] rwc-_-_ DCW [10:9] rwc-_-_ DMS [8:7] rwc-_-_ DDW [6:5] rwc-_-_ DRRS [4:0] rwc-_-_ DCR3. A:0398h DBMR [31:16] rwc-_-_ DEMR [15:0] rwc-_-_ 10.3.5.2 External ...
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EMI. Field Addr (A:) Name Bit [x:y] Type ETRCSL [4] rls-crw-i3 ETWCSL [3] rls-crw-i3 TXPSRCS [2] rls-crw-i3 L TXPSWC [1] rls-crw-i3 SL TXHSRCS [0] rls-crw-i3 L 10.3.5.3 External Memory Interface Status Register Interrupt Enables (EMI.) Table 10-19. External Memory Interface ...
Page 118
EMI. Field Addr (A:) Name Bit [x:y] Type RPI1WER [7] rls-crw-_ RSL RPI2WER [6] rls-crw-_ RSL TDI1ERR [5] rls-crw-_ SL TDI2ERR [4] rls-crw-_ SL TEI1ERR [3] rls-crw-_ SL TEI2ERR [2] rls-crw-_ SL TPI1ERR [1] rls-crw-_ SL TPI2ERR [0] rls-crw-_ SL ...
Page 119
EMA. Field Addr (A:) Name Bit [x:y] Type TPCWC [12:10] rwc-_-_ TL [9:0] rwc-_-_ WAR. A:03C4h RSVD [31:0] WDR. A:03C8h EMWD [31:0] woc-_-_ WSR1. A:03CCh RSVD [31:17] WQNFS [16] ros-_-i3 RSVD [15:7] WFES [6] ros-_-i3 RSVD [5:0] WSR2. A:03D0h RSVD ...
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EMA. Field Addr (A:) Name Bit [x:y] Type RSVD [4:0] WSRIE1. A:03D8h RSVD [31:19] WPNRIE [18] rwc-_-i3 RSVD [17] WQNFIE [16] rwc-_-i3 RSVD [15:8] WFOIE [7] rwc-_-i3 WFEIE [6] rwc-_-i3 WTOIE [5] rwc-_-i3 RSVD [4:0] 10.3.6.2 Read Registers (EMA.) Table ...
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EMA. Field Addr (A:) Name Bit [x:y] Type RSVD [5:0] RSR2. A:03F0h RSVD [31] RQL [30:21] ros-_-_ RSVD [20:19] RQRP [18:10] ros-_-_ RFL [9:0] ros-_-_ RSRL1. A:03F4h RSVD [31:19] [18] rls-crw-i3 Read Preempted by New Request Status Latch = “1” ...
Page 122
Encap BERT Registers (EB.) Table 10-23. Encap BERT Registers (EB.) EB. Field Addr (A:) Name Bit [x:y] Type BCR. A:0400h RSVD [31:8] PMUM [7] rwc-_-_ LPMU [6] rwc-_-_ RNPL [5] rwc-_-_ RPIC [4] rwc-_-_ MPR [3] rwc-_-_ APRD [2] ...
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EB. Field Addr (A:) Name Bit [x:y] Type BSPR. A:0408h BSP [31:0] rwc-_-_ TEICR. A:0410h RSVD [31:6] TEIR [5:3] rwc-_-_ BEI [2] rwc-_-_ TSEI [1] rwc-_-_ MEIMS [0] rwc-_-_ BSR. A:0414h RSVD [31:2] BEC [1] ros-_-i3 OOS [0] ros-_-i3 BSRL. ...
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Decap BERT Registers (DB.) Table 10-24. Decap BERT Registers (DB.) DB. Field Addr (A:) Name Bit [x:y] Type BCR. A:0400h RSVD [31:8] PMUM [7] rwc-_-_ LPMU [6] rwc-_-_ RNPL [5] rwc-_-_ RPIC [4] rwc-_-_ MPR [3] rwc-_-_ APRD [2] ...
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DB. Field Addr (A:) Name Bit [x:y] Type BSPR1. A:0408h BSP [31:0] rwc-_-_ TEICR. A:0410h RSVD [31:6] TEIR [5:3] rwc-_-_ BEI [2] rwc-_-_ TSEI [1] rwc-_-_ MEIMS [0] rwc-_-_ BSR. A:0414h RSVD [31:2] BEC [1] ros-_-i3 OOS [0] ros-_-i3 BSRL. ...
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Miscellaneous Diagnostic Registers (MD.) Table 10-25. Miscellaneous Diagnostic Registers (MD.) MD. Field Addr (A:) Name Bit [x:y] Type DCR. A:0480h RSVD [31:1] MBE [0] rwc-_-_ EBCR. A:0484h RSVD [31:24] ETBE [24] rwc-_-_ ETBBS [23:16] rwc-_-_ RSVD [15:9] ERBE [8] ...
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Test Registers (TST.) Table 10-26. Test Registers (TST.) TST. Field Addr (A:) Name Bit [x:y] Type GTR1. A:0600h RSVD [31:7] CTCE [6] rwc-_-_ CWLUPM [5] rwc-_-_ SOEE [4] rwc-_-_ COEE [3] rwc-_-_ MTPOE [2] rwc-_-_ MCRS [1] rwc-_-_ INTE ...
Page 128
TST. Field Addr (A:) Name Bit [x:y] Type BTSR4. A:0630h TEIBTS [31:0] BTSR5. A:0634h EMIBTS [31:0] BTSR6. A:0638h SBIBTS [31:0] CTCR1. A:0640h PD [31:28] rwc-_-_ RST [27:24] rwc-_-_ TCS [23:22] rwc-_-_ IRA [21:19] rwc-_-_ VRA [18:17] rwc-_-_ RSVD [16:7] PMIA ...
Page 129
TST. Field Addr (A:) Name Bit [x:y] Type FID. A:06FCh FRI [31:0] ros-_-_ 10.3.11 Clock Recovery Registers (CR.) These registers are defined by the S132 Clock Recovery firmware load (according to the firmware revision). 10.3.12 MAC Registers (M.) Table 10-27. ...
Page 130
Addr (A:) M. Field Name Bit [x:y] MDC_CLK_DIV [20:18] rwc-_-_ FCS_REMOVE [17] rwc-_-_ LGTH_FRM_DIS [16] rwc-_-_ RX_BUF_OFFSET [15:14] rwc-_-_ PAUSE_EN [13] rwc-_-_ RETRY_TST [12] rwc-_-_ RSVD [11] GIG_MODE_EN [10] rwc-_-_ EXT_AMATCHEN [9] rwc-_-_ RX_1536FRMS [8] rwc-_-_ UNI_HSH_EN [7] rwc-_-_ MULT_HSH_EN ...
Page 131
Addr (A:) M. Field Name Bit [x:y] TX_COMPLETE [5] rls-cow-_ Reserved. [4] rls-cow-_ Reserved. TX_BUF_EXH [3] rls-cow-_ Reserved. TX_GO [2] rls-cow-_ Reserved. TX_RETRY_EXC [1] rls-cow-_ Reserved. TX_COL TX_USED [0] rls-cow-_ Reserved. RX_QPTR. A:0C18h RX_BUF_QBA [31:2] rwc-_-_ RSVD [1:0] TX_QPTR. A:0C1Ch ...
Page 132
Addr (A:) M. Field Name Bit [x:y] RSVD [9:8] EN_IRQ_TX_DONE [7] woc-_-_ EN_IRQ_TX_ERROR [6] woc-_-_ [5] woc-_-_ EN_IRQ_RETRY_EXC EN_IRQ_TX_URUN [4] woc-_-_ EN_IRQ_TX_USED [3] woc-_-_ EN_IRQ_RX_USED [2] woc-_-_ EN_IRQ_RX_DONE [1] woc-_-_ [0] woc-_-i3 EN_IRQ_MAN_DONE IRQ_DISABLE. A:0C2Ch RSVD [31:18] RSVD [17:16] DIS_IRQ_EXT_INT ...
Page 133
Addr (A:) M. Field Name Bit [x:y] MSK_IRQ_RX_USED [2] ros-_-_ MSK_IRQ_RX_DONE [1] ros-_-_ MSK_IRQ_MAN_D [0] ros-_-_ ONE PHY_MAN. A:0C34h PHY_SET3 [31] rwc-_-_ PHY_CL22 [30] rwc-_-_ PHY_SET2 [29:28] rwc-_-_ PHY_ADDR [27:23] rwc-_-_ PHY_REG_ADDR [22:18] rwc-_-_ PHY_SET1 [17:16] rwc-_-_ PHY_DATA_WR [15:0] rwc-_-_ ...
Page 134
Addr (A:) M. Field Name Bit [x:y] LADDR4_TOP. A:0CA4h RSVD [31:16] SPEC_ADD4_TOP [15:0] rwc-_-_ ID_CHECK1. A:0CA8h EN_TYPE_ID_M1 [31] rwc-_-_ RSVD [30:16] TYPE_ID_M1 [15:0] rwc-_-_ ID_CHECK2. A:0CACh EN_TYPE_ID_M2 [31] rwc-_-_ RSVD [30:16] TYPE_ID_M2 [15:0] rwc-_-_ ID_CHECK3. A:0CB0h EN_TYPE_ID_M3 [31] rwc-_-_ RSVD ...
Page 135
Addr (A:) M. Field Name Bit [x:y] MULTICAST_TX. A:0D10h MLTCST_TX [31:0] rcs-cor-sc Multicast Frames Transmitted = # transmitted Ethernet Multicast STATS_PAUSE_TX A:0D14h . RSVD [31:16] [15:0] rcs-cor-sc Reserved. PAUSE_TX FRAME64_TX. A:0D18h [31:0] rcs-cor-sc 64 Byte Frames Transmitted = # transmitted ...
Page 136
Addr (A:) M. Field Name Bit [x:y] LATE_COL [9:0] rcs-cor-sc Reserved. STATS_DEF_TX. A:0D48h RSVD [32:18] DEF_TX_FRMS [17:0] rcs-cor-sc Reserved. STATS_CRS_ERR A:0D4Ch ORS. RSVD [31:10] CRS_ERRORS [9:0] rcs-cor-sc Reserved. OCT_RX_BOT. A:0D50h [31:0] rcs-cor-sc Received Octets in Frame [31: octets ...
Page 137
Addr (A:) M. Field Name Bit [x:y] FRAME512_RX. A:0D78h 512TO1023B_RX [31:0] rcs-cor-sc 512 to 1023 Byte Frames Received = # received frames with 512 to FRAME1024_RX. A:0D7Ch [31:0] rcs-cor-sc 1024 to 1518 Byte Frames Received = # received frames with ...
Page 138
Addr (A:) M. Field Name Bit [x:y] RX_SYM_ERR [9:0] rcs-cor-sc Received Symbol Errors = # received frames with input pin RX_ER = 1 STATS_ALIGN_ER A:0D9Ch RORS. RSVD [31:10] [9:0] rcs-cor-sc Alignment Errors = # received frames with a length that ...
Page 139
TXSCn Addr (A:) Field Name Bit [x:y] Type CTS4 [15:12] rwd-_-_ CTS5 [11:8] rwd-_-_ CTS6 [7:4] rwd-_-_ CTS7 [3:0] rwd-_-_ CR2. A:1004h CTS8 [31:28] rwd-_-_ CTS9 [27:24] rwd-_-_ CTS10 [23:20] rwd-_-_ CTS11 [19:16] rwd-_-_ CTS12 [15:12] rwd-_-_ CTS13 [11:8] rwd-_-_ ...
Page 140
RXSCn. Addr (A:) Field Name Bit [x:y] Type CTS6 [7:4] rwd-_-_ CTS7 [3:0] rwd-_-_ CR2. A:1204h CTS8 [31:28] rwd-_-_ CTS9 [27:24] rwd-_-_ CTS10 [23:20] rwd-_-_ CTS11 [19:16] rwd-_-_ CTS12 [15:12] rwd-_-_ CTS13 [11:8] rwd-_-_ CTS14 [7:4] rwd-_-_ CTS15 [3:0] rwd-_-_ ...
Page 141
Pn. Field Addr (A:) Name Bit [x:y] Type FFS [27] rwc-_-_ MFS [26:25] rwc-_-_ BFD [24:23] rwc-_-_ BPF [22:18] rwc-_-_ DP [17] rwc-_-_ DOSOT [16] rwc-_-_ RSVD [15:0] PTCR2. A:2004h RSVD [31:8] PRPTLL [9] rwc-_-_ TIOE [8] rwc-_-_ TCE [7] ...
Page 142
Pn. Field Addr (A:) Name Bit [x:y] Type TDS [5] rwc-_-_ TOES [4] rwc-_-_ TIES [3] rwc-_-_ TSS [2:0] rwc-_-_ PTCR3. A:2008h PRPTTSL [31:0] rwc-_-_ 10.3.15.2 Port n Transmit Status Registers (Pn.) Table 10-31. Port n Transmit Status Registers (Pn.) ...
Page 143
Pn. Field Addr (A:) Name Bit [x:y] Type CTS13 [11:8] ros-_-_ CTS14 [7:4] ros-_-_ CTS15 [3:0] ros-_-_ PTSR3. A:2028h CTS16 [31:28] ros-_-_ CTS17 [27:24] ros-_-_ CTS18 [23:20] ros-_-_ CTS19 [19:16] ros-_-_ CTS20 [15:12] ros-_-_ CTS21 [11:8] ros-_-_ CTS22 [7:4] ros-_-_ ...
Page 144
Port n Receive Configuration Registers (Pn.) Table 10-34. Port n Receive Configuration Registers (Pn.) Pn. Field Addr (A:) Name Bit [x:y] Type PRCR1. A:2040h DR [31] rwc-_-_ RSVD [30:29] SFS [28] rwc-_-_ FFS [27] rwc-_-_ MFS [26:25] rwc-_-_ BFD ...
Page 145
Pn. Field Addr (A:) Name Bit [x:y] Type DBVSE [14] rwc-_-_ LB [13] rwc-_-_ LBSS [12] rwc-_-_ SPL [11:1] rwc-_-_ RSVD [0] PRCR2. A:2044h RSVD [31:7] RSTS [6] rwc-_-_ RDS [5] rwc-_-_ RSVD [4] RIES [3] rwc-_-_ RSVD [2:1] RSS ...
Page 146
Pn. Field Addr (A:) Name Bit [x:y] Type RSVD [15:13] TSGN0C [12:0] rwc-_-_ 10.3.15.6 Port n Receive Status Registers (Pn.) Table 10-35. Port n Receive Status Registers (Pn.) Pn. Field Addr (A:) Name Bit [x:y] Type PRSR1. A:2060h CTS0 [31:28] ...
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Pn. Field Addr (A:) Name Bit [x:y] Type CTS30 [7:4] ros-_-_ CTS31 [3:0] ros-_-_ 10.3.15.7 Port n Receive Status Register Latches (Pn.) Table 10-36. Port n Receive Status Register Latches (Pn.) Pn. Field Addr (A:) Name Bit [x:y] Type PRSRL. ...
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Register Guide The Register Guide Section provides example settings for some of the more common applications, especially for applications in which one register setting determines which settings are valid for other related registers. The S132 registers and their functional ...
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Global Packet Settings Table 10-39. Global Ethernet MAC (M.) Control Register Settings (Values are in hex) Bit # Register Bit Name r/w Val M.NET_CONTROL - Network Control Register 10 TX_HALT START_TX MAN_PORT_EN rw ...
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Table 10-40. Global Ethernet Packet Classification (PC.) Settings Register Functional Description Ethernet CR17 - CR19 Ethernet DA1 and DA2 CR1.DBTP Broadcast TDMoP Pkt Discard CR1.DBCP Broadcast CPU Pkt Discard CR1.DPS9 Unknown Ethernet DA Discard CR3.VITPID VLAN Inner Tag Protocol ID ...
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Table 10-41. Valid UDP BID Location and UDP Protocol Type Settings UDP BID Location Test BID Test Settings Mode PC.CR1 UBIDLS 1 All Bundles “16-bit auto discover” Per-Bundle setting “16-bit Source Port” B Per-Bundle setting: 0 ...
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SAT Bundle Settings Table 10-43. SAT Bundle Settings Reg-bit Bit Name BCDR1 23 LBCAI 22:21 PMT 20:10 PMS SCSCFPD R [0] [0] 8 SCSNRE R [1] ...
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CES without CAS Bundle Settings Table 10-45. CES without CAS Bundle Settings Reg-bit Bit Abbrev BCDR1 23 LBCAI 22:21 PMT 20:10 PMS SCSCFPD R [0] [0] ...
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CES with CAS Bundle Settings Table 10-47. CES with CAS Bundle Settings Reg-bit Bit Abbrev BCDR1 23 LBCAI 22:21 PMT 20:10 PMS SCSCFPD R [0] [0] ...
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Unstructured HDLC Bundle (any Line Rate) Settings Table 10-49. Unstructured HDLC Bundle (any Line Rate) Settings Reg-bit Bit Abbrev BCDR1 23 LBCAI 22:21 PMT 20:10 PMS ...
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Structured Nx64 Kb/s HDLC Bundle Settings Table 10-50. Structured Nx64 Kb/s HDLC Bundle Settings Reg-bit Bit Abbrev BCDR1 23 LBCAI 22:21 PMT 20:10 PMS SCSCFPD NA ...
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Structured 16 Kb Kb/s HDLC Bundle Settings Table 10-51. Structured 16 Kb Kb/s HDLC Bundle Settings Reg-bit Bit Abbrev BCDR1 23 LBCAI 22:21 PMT 20:10 PMS ...
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Clock Only Bundle Settings 10.4.2.7.1 Combined RXP and TXP (Bidirectional) Clock Only Bundle Settings Table 10-52. Combined RXP and TXP (Bidirectional) Clock Only Bundle Settings Reg-bit Bit Abbrev BCDR1 23 LBCAI 22:21 PMT ...
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RXP (Unidirectional) Clock Only Bundle Settings Table 10-53. RXP (Unidirectional) Clock Only Bundle Settings Reg-bit Bit Abbrev BCDR1 23 LBCAI 22:21 PMT 20:10 PMS SCSCFPD R ...
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TXP (Unidirectional) Clock Only Bundle Settings Table 10-54. TXP (Unidirectional) Clock Only Bundle Settings Reg-bit Bit Abbrev BCDR1 23 LBCAI 22:21 PMT 20:10 PMS SCSCFPD NA ...
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RXP PW Debug” Bundle Settings The minimum Bundle settings that must be configured to properly detect packets for CPU Debug RXP PW Bundles are provided in Table 10-55. In the table, “NR” indicates “Not Required”. An “NR” value ...
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In-band VCCV OAM Connection Settings When In-band VCCV OAM is used it is always part of a CES, SAT, HDLC or Clock Only Bundle. The In-band VCCV connection can enabled before all of the Bundle function/settings ...
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Send to CPU Settings There are several RXP packet conditions that can be used to forward packets to the CPU that have been described in previous Register Guide sections. conditions using an abbreviated detected condition description. Table 10-58. “Send ...
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Table 10-60. TDM Port “n” Register Settings for T1 Applications (Pn 31) Reg-bit Bit Name RT SAT CES no CAS TXSCn.CR1 - CR4 31 CTS0-CTS23 RXSCn.CR1 - CR4 31 CTS0-CTS23 PTCR1. 31 ...
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Table 10-61. TDM Port “n” Register Settings for E1 Applications (Pn 31) Reg-bit Bit Name RT SAT CES no CAS TXSCn.CR1 - CR4 31 CTS0-CTS23 RXSCn.CR1 - CR4 31 CTS0-CTS23 PTCR1. 31 ...
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Table 10-62. TDM Port “n” Register Settings for non-T1/E1 Applications (Pn 31) Reg-bit Bit Name RT SAT Bit Name Description PTCR1 Data path Reset 28 SFS R 0 Structure Format Select 27 ...
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Status Monitoring 10.4.5.1 Ethernet Port Monitoring Table 10-63. Ethernet MAC Status Registers (M.) Bit # Register Bit Name r/w NET_CONTROL - Network Control Register 14 RD_SNAP rw 13 TAKE_SNAP wo 5 STATS_CLR wo NET_STATUS - Network Status Register 2 ...
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Global Packet Classifier Monitoring Control Table 10-65. Global Packet Classifier Monitoring Settings (PC.) Register Packet Classifier Function CPCR.CPC Good Packet Count PCECR.UICPEC UDP & IP Pkt FCS Error Count CR1.UICECS UDP & IP FCS Error Select SPCR.SPC Stray Packet ...
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Table 10-69. RXP Bundle Status/Statistics Registers Bundle Register Status Bits Select B.BDSCR B.BDSR1 JBLPDSL PDC B.BDSR2 JBEC B.BDSR3 JBLL JBHL B.BDSR4 GPRXC B.BDSR5 SCJPC B.BDSR6 SCRPC B.BDSR7 SCPSESL PLESL SCJBEPDSL JBCL LBD RBD DMD FBD B.BDSR8 SCMPC B.BDSR9 SCRBPC - ...
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INVALID 128 INVALID INVALID 32 INVALID Note: “INVALID” means that the packet size would exceed the 2 Kbyte maximum packet size expected ...
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JTAG INFORMATION This device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The device contains the following items, which meet the requirements set by the IEEE 1149.1 Standard Test ...
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DC ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Input, Bi-directional or Open Drain Output Lead with Respect to VSS (except VDD) Supply Voltage (VDD33) with Respect to VSS Supply Voltage (VDD18) with Respect to VSS Ambient Operating ...
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Table 12-2. DC Electrical Characteristics (T Parameter VDD33 I/O Supply Current (VDD33 = 3.465V) VDDQ I/O + VDDP I/O Supply Current (VDD = 2.625) VDD18 Supply Current (VDD18 = 1.89) AVDD Supply Current ( AVDD = 1.89) CVDD Supply Current ...
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Figure 13-1. MPC870-like processor CPU Interface Write Cycle SYSCLK PCS_N PA[13:2] PD[31:0] PRW_N PTA_N Figure 13-2. MPC870-like processor CPU Interface Read Cycle SYSCLK PCS_N PA[13:2] PD[31:0] PRW_N PTA_N Figure 13-3. MPC8313-like processor CPU Interface Write Cycle SYSCLK PCS_N t 15 ...
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Figure 13-4. MPC8313-like processor CPU Interface Read Cycle SYSCLK PCS_N t 15 PALE PA[13:2] PD[15:0] PRW_N PTA_N 13.2 TDM Interface Table 13-2. TDM Ports PARAMETER TCLKO Output Period TSYNC, RSYNC, RDAT, RSIG input setup to TCLKO TSYNC, RSYNC, RDAT, RSIG ...
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Figure 13-5. TDM Port using Single Clock (TCLKO), positive edge timing (RSS = 1, TIES = RIES = 0) TCLKOn RDATn,RSYNCn,RSIGn 1 TSYNCn 2 TSYNCn TDATn, TSIGn 1 Notes: TSYNC programmed Output 2 TSYNC programmed to be ...
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MAC Interface 13.3.1 GMII Interface Table 13-3. GMII Transmit Timing PARAMETER GTXCLK Output Period GTXCLK Stability GTXCLK Duty Cycle TXD,TXEN, & TXER valid after rising edge GTXCLK TXD,TXEN, & TXER hold after rising edge GTXCLK 1 Notes: The rise ...
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Figure 13-9. MII Transmit Timing TXCLK TXD, TXEN, TXER Table 13-6. MII Receive Timing PARAMETER RXCLK input Period TXCLK Duty Cycle RXDV,RXD, & RXER setup prior to RXCLK RXDV, RXD, RXER hold after RXCLK 1 Notes: Input low and input ...
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Figure 13-11. DDR SDRAM Timing P0 SD_CLK SD_CLK WRITE t1 Address / Control SDATA SD_UDQS t7 SD_LDQS SD_UDM SD_LDM READ SD_CLK SD_CLK SD_UDQS SD_LDQS SDATA 19-4750; Rev 1; 07/ t14 t13 t9 t10 t12 ...
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PIN ASSIGNMENT Table 14-1. Pins Sorted by Signal Name Signal Ball# Signal AVDD A6 PA[13] AVSS A7 PA[2] CMNCLK AC10 PA[3] COL H24 PA[4] CRS H25 PA[5] CVDD AF9 PA[6] CVSS AF8 PA[7] DDRCLK B7 PA[8] EPHYRST_N H26 PA[9] ...
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Signal Ball# Signal RSIG23 Y13 RSYNC7 RSIG24 Y14 RSYNC8 RSIG25 Y15 RSYNC9 RSIG26 Y16 RXCLK RSIG27 Y17 RXD[0] RSIG28 Y19 RXD[1] RSIG29 Y20 RXD[2] RSIG3 J7 RXD[3] RSIG30 Y21 RXD[4] RSIG31 AC22 RXD[5] RSIG4 K7 RXD[6] RSIG5 L7 RXD[7] RSIG6 ...
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Signal Ball# Signal TSIG20 AD7 TSYNC5 TSIG21 AC8 TSYNC6 TSIG22 AD11 TSYNC7 TSIG23 AC12 TSYNC8 TSIG24 AC13 TSYNC9 TSIG25 AC14 TXCLK TSIG26 AD16 TXD[0] TSIG27 AD17 TXD[1] TSIG28 AC18 TXD[2] TSIG29 AC19 TXD[3] TSIG3 F4 TXD[4] TSIG30 AC20 TXD[5] TSIG31 ...
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Signal Ball# Signal VSS L12 VSS VSS L13 VSS VSS L14 VSS VSS L15 VSS VSS L16 VSS VSS L17 VSS VSS L18 VSS VSS L22 VSS VSS L9 VSS VSS M10 VSS VSS M11 VSS VSS M12 VSS VSS ...
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Table 14-2. Pins Sorted by Ball Grid Array - Ball Number Ball# Signal A1 VDD33 A10 SDDQ[14] A11 SDDQ[11] A12 SDDQ[10] A13 SDDQ[8] AB10 A14 SDUDM AB11 A15 SDCLK_N AB12 A16 SDCLK AB13 A17 SDA[12] AB14 A18 SDA[8] AB15 A19 ...
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Ball# Signal B22 JTMS B23 JTRST_N B24 B25 VDD33 B26 ETHCLK B3 TDAT1 B4 TSYNC0 B5 TDAT0 B6 VSS B7 DDRCLK B8 SMTI B9 VDDQ C1 TCLKO3 C10 SDDQ[1] C11 SDDQ[3] C12 SDDQ[5] C13 SDLDQS C14 VSSQ C15 SDWE_N C16 ...
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Ball# Signal K19 VDD18 K2 TSIG8 K20 K21 K22 VSS K23 TXERR K24 TXD[5] K25 TXD[4] K26 GTXCLK K3 RCLK8 K4 RCLK6 K5 RSYNC5 K6 RDAT4 K7 RSIG4 K8 VDD18 K9 VSS L1 TCLKO9 L10 VSS L11 VSS L12 VSS ...
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Ball# Signal V15 VSS V16 VSS V17 VSS V18 VSS V19 VDD18 V2 TDAT11 V20 MT[10] V21 PD[26] V22 PD[27] V23 PD[28] V24 PD[29] V25 PD[30] V26 PD[31] V3 TDAT12 V4 RCLK14 V5 RSYNC15 V6 RDAT16 V7 RSIG16 19-4750; Rev ...
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Table 14-3. Pin Assignments according to Device Outline ...
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PACKAGE INFORMATION The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE 676 TEPBGA (27mm x 27mm) Figure 15-1. 676-Ball TEPBGA ...
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THERMAL INFORMATION Table 16-1. Thermal Package Information Parameter Target Ambient Temperature Range Die Junction Temperature Range Theta-JA, Still Air Theta-JC, Still Air Psi Jt (Junction to Top of Case) Note 1: Theta-JA is based on the package mounted on ...
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