DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 125

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

19-4750; Rev 1; 07/11
DB. Field
Name
BSPR1.
BSP
TEICR.
RSVD
TEIR
BEI
TSEI
MEIMS
BSR.
RSVD
BEC
OOS
BSRL.
RSVD
BEL
BECL
OOSL
BSRIE.
RSVD
BEIE
BECIE
OOSIE
RBECR.
RSVD
BEC
RBCR.
BC
TSTCR.
RSVD
Addr (A:)
Bit [x:y]
A:0408h
A:0410h
A:0414h
A:0418h
A:041Ch
A:0420h
A:0424h
A:0430h
[31:24]
[31:0] rwc-_-_
[31:6]
[31:2]
[31:3]
[31:3]
[23:0] rcs-cor-sc
[31:0] rcs-cor-sc
[31:0]
[5:3] rwc-_-_
[2] rwc-_-_
[1] rwc-_-_
[0] rwc-_-_
[1] ros-_-i3
[0] ros-_-i3
[2] rls-crw-i3
[1] rls-crw-i3
[0] rls-crw-i3
[2] rwc-_-i3
[1] rwc-_-i3
[0] rwc-_-i3
Type
Description
BERT Seed / Pattern Register. Default: 0x00.00.00.00
BERT Seed/Pattern specifies the seed value for the transmit PRBS pattern, or
the transmit and receive Repetitive Pattern. BSP[31] is the 1
the expected 1
Transmit Error Insertion Control Register. Default: 0x00.00.00.00
Reserved.
Transmit Error Insertion Rate specifies the rate at which errors are inserted in
the RXP TDM BERT Generator output data stream (TSEI = 0). One out of every
10
Error Insertion Rate function. TEIR = 1 results in every 10th bit being inverted. If
this register is written to during the middle of an error insertion process, the TEIR
insertion rate is updated after the next error is inserted.
Bit Error Insertion Enable = “0” disables error insertion (disables TEIR & TSEI)
Transmit Single Error Insert A 0 to 1 transition forces a single bit error in the
RXP TDM BERT Generator output stream (TEIR = 0). If this bit transitions more
than once between error insertion opportunities, only one error will be inserted.
Reserved.
BERT Status Register. Default: 0x00.00.00.00
Reserved.
Performance Monitoring Update Status = “1” indicates the RXP Packet BERT
Monitor bit error count > 0 (DB.RBECR.BEC).
Out Of Synchronization = “1” indicates the RXP Packet BERT Monitor is not
synchronized to the incoming pattern.
BERT Status Register Latch. Default: 0x00.00.00.00
Reserved.
Bit Error Latched = “1” when one or more bit errors are detected.
Bit Error Count Latched = “1” when DB.BSR.BEC transitions from 0 to 1.
Out Of Synchronization Latched = “1” when DB.BSR.OOS changes state.
BERT Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Bit Error Interrupt Enable. The combination of BEIE = 1 and DB.BSRL.BEL = 1
forces G.GSR1.EBS = 1.
Bit Error Count Interrupt Enable. The combination of BECIE = 1 and
DB.BSRL.BECL = 1 forces G.GSR1.EBS = 1.
Out Of Synchronization Interrupt Enable. The combination of OOSIE = 1 and
DB.BSRL.OOSL = 1 forces G.GSR1.EBS = 1.
Receive Bit Error Count Register. Default: 0x00.00.00.00
Reserved.
Bit Error Count = # bit errors during the previous update period (DB.BCR.LPMU)
but not including errors during an Out of Sync condition (DB.BSR.OOS = 1).
Receive Bit Count Register. Default: 0x00.00.00.00
Bit Count = # received bits during the previous update period (DB.BCR.LPMU)
but not including errors during an Out of Sync condition (DB.BSR.OOS = 1).
Test Control Register. Default: 0x00.00.00.00
Reserved.
k
bits is inverted where k = TEIR and k > 0. TEIR = 0 disables the Transmit
st
receive bit. BSP is ignored when the QRSS Pattern is enabled.
DS34S132 DATA SHEET
st
transmitted bit and
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