DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 148

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

10.4 Register Guide
The Register Guide Section provides example settings for some of the more common applications, especially for
applications in which one register setting determines which settings are valid for other related registers. The S132
registers and their functional operation cannot be fully understood without also reading the Functional Description
and Register Definition sections. When those two sections are understood this section enables an S132 user to
quickly identify interactions and settings that must be made for particular applications.
Figure 10-1
depict the flow of RXP and TXP packet data. The boxes each represent one of the Register Guide sub-sections
and give a high level view of how the sub-sections relate to each other.
Figure 10-1. Register Guide High Level Diagram
Throughout this section example register values are presented as decimal values except when the “0x” notation is
used to identify a hex value (e.g. 0x17) or when the letter “b” follows a “1” or “0” to indicate a binary value (e.g.
“10b”). This means that a “5” when indicated for a 3-bit register field equates to “101” binary (register bits are
always programmed using binary equivalent values). Register bit numbers, paragraph text and equations are
always indicated using decimal values (e.g. for “bit 10”, the value “10” is a decimal value).
An “x” value (by itself) is used in the tables that follow to indicate “any valid value”. In many cases the only “valid
values” are listed in the “Comment” column of the table. If the “Comment column” does not provide specific values,
then “any” value is legal. Dark shading and/or “NA” are used to identify rows or cells within each table that are “Not
Applicable” to the identified application. When a Write register bit is identified in this way, the “0” value should be
written to that register unless specified otherwise. When a Read register bit is identified in this way, the returned
register bit value should be ignored.
19-4750; Rev 1; 07/11
To CPU
From
To/From
CPU
Ports
TDM
provides a high level view of how the Register Guide sub-sections relate to each other. The arrows
Settings
Send to
Port Settings
10.4.4 TDM
10.4.3
CPU
HDLC/Clock-
SAT/CES/
only
Non-PW CPU packets (e.g. special Ethernet Types & error conditions)
10.4.2 Bundle and OAM Bundle Settings
CPU TXP Packets
SAT, CES, HDLC &
Clock-Only Bundles
10.4.5 Status Monitoring
10.4.6 SDRAM settings
TXP SAT/
CES/HDLC/
Clock Only
Bundle pkts
RXP Bundle/
OAM Bundle
Packets
TXP Packets
Packet Settings
10.4.1 Global
DS34S132 DATA SHEET
Packets
RXP
148 of 194
Ethernet
To/From
Port