DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 24

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

19-4750; Rev1; 7/11
Pin Name
PRWCTRL
PTA_N
PWIDTH
PINT_N
External Memory Interface – DDR SDRAM
SDCLK,
SDCLK_N
SDCLKEN
SDCS_N
SDRAS_N
SDCAS_N
SDWE_N
SDBA[1:0]
SDA[13:0]
SDDQ[15:0]
SDLDM
SDUDM
SDLDQS
SDUDQS
Type
Oz
Oz
Oz
Oz
Oz
Oz
Oz
Oz
Oz
Oz
Oz
Oz
Oz
Oz
IO
I
I
Pin Description
Processor Read/Write Control.
0 = PRW is high for a write, low for a read (PQ II Pro mode)
1 = PRW is low for a write, high for a read (PQ I mode)
Processor Transfer Acknowledge. This signal indicates to the processor on a read
that data is valid on the data bus. On a write, it indicates that the DS34S132 is ready
for a new transaction. This signal is synchronous to SYSCLK since the PowerQuicc I
requires it. This signal requires an external pull-up. On the PowerQuicc I, the PTA_N
is used as a data valid signal and therefore must be coincident with the data on read
accesses (i.e. it may not be early.)
Processor Bus Width
0 = 16-bit mode
1 = 32-bit mode
Processor Interrupt. When the bit configurable Interrupt Inactive Mode is ‘0’, this pin
is active low, asynchronous to SYSCLK and is high impedance when not active.
When the bit configurable Interrupt Inactive Mode is ‘1’, this pin is active low,
asynchronous to SYSCLK and drives high when no interrupts are active.
SDRAM Clock. SDCLK and SDCLK_N are differential clock outputs. (Both pins are
referenced collectively as SDCLK.) All address and control input signals are sampled
on the positive edge of SDCLK and negative edge of SDCLK. Output (write) data is
referenced to the rising edge and falling edge of SDCLK.
SDRAM Clock Enable. Active High. SDCLKEN must be active throughout DDR
SDRAM READ and WRITE accesses.
SDRAM Chip Select. All commands are masked when SDCS_N is registered high.
SDCS_N provides for external bank selection on systems with multiple banks. SDCS-
_N is considered part of the command code.
SDRAM Row Address Strobe. Active low output, used to latch the row address on
rising edge of SDCLK. It is used with commands for Bank Activate, Precharge, and
Mode Register Write.
SDRAM Column Address Strobe. Active low output, used to latch the column
address on the rising edge of SDCLK. It is used with commands for Bank Activate,
Precharge, and Mode Register Write.
SDRAM Write Enable. This active low output enables write operation and auto
precharge.
SDRAM Bank Select. These 2 bits select 1 of 4 banks for the read/write/precharge
operations.
SDRAM Address. The 14 pins of the SDRAM address bus output the row address
first, followed by the column address. The row address is determined by SDA[0] to
SDA[13] at the rising edge of clock. Column address is determined by SDA[0]-SDA[9]
at the rising edge of the clock. SDA[10] is used as an auto-precharge signal.
SDRAM Data Bus. The 16 pins of the SDRAM data bus are inputs for read
operations and outputs for write operations. At all other times, these pins are high-
impedance.
SDRAM Lower Data Mask. SDLDM is an active high output mask signal for write
data. SDLDM is updated on both edges of SDLDQS. SD_LDM corresponds to data
on SDATA7-SDATA0.
SDRAM Upper Data Mask. SDUDM is an active high output mask signal for write
data. SDUDM is updated on both edges of SDUDQS. SDUDM corresponds to data
on SDATA15-SDATA8.
SDRAM Lower Data Strobe. Output with write data, input with read data. SDLDQS
corresponds to data on SDATA7-SDATA0.
SDRAM Upper Data Strobe. Output with write data, input with read data. SDUDQS
corresponds to data on SDATA15-SDATA8.
DS34S132 DATA SHEET
24 of 194