DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 3

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

10
19-4750; Rev1; 7/11
9.4
9.5
9.6
10.1 Register Block Address Ranges ............................................................................................................. 74
10.2 Register Address Reference List ............................................................................................................ 75
10.3 Register Definitions ................................................................................................................................ 83
Device Registers .......................................................................................................................................... 74
9.3.3
9.4.1
9.4.2
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
10.3.1 Global Registers (G.) ..................................................................................................................... 83
10.3.2 Bundle Registers (B.) ..................................................................................................................... 89
10.3.3 Jitter Buffer Registers (JB.) .......................................................................................................... 104
10.3.4 Packet Classifier Registers (PC.) ................................................................................................. 110
10.3.5 External Memory Interface Registers (EMI.) ................................................................................. 115
10.3.6 External Memory Access Registers (EMA.) .................................................................................. 118
10.3.7 Encap BERT Registers (EB.) ....................................................................................................... 122
10.3.8 Decap BERT Registers (DB.) ....................................................................................................... 124
10.3.9 Miscellaneous Diagnostic Registers (MD.) ................................................................................... 126
10.3.10 Test Registers (TST.) ................................................................................................................... 127
10.3.11 Clock Recovery Registers (CR.) ................................................................................................... 129
9.3.3.1
9.3.3.2
9.3.3.3
9.3.3.4
CPU Packet Interface ............................................................................................................................ 63
Clock Recovery Functions ..................................................................................................................... 68
Miscellaneous Global Functions ............................................................................................................. 68
9.6.3.1
10.3.1.1 Global Configuration Registers (G.) ........................................................................................ 83
10.3.1.2 Global Status Registers (G.) ................................................................................................... 86
10.3.1.3 Global Status Register Interrupt Enables (G.) ......................................................................... 88
10.3.2.1 Bundle Reset Registers (B.) ................................................................................................... 89
10.3.2.2 Bundle Data Control Registers (B.) ......................................................................................... 90
10.3.2.3 Bundle Data Registers (B.) ..................................................................................................... 91
10.3.2.4 Bundle Status Latch Registers (B.) ......................................................................................... 97
10.3.2.5 Bundle Status Register Interrupt Enables (B.) ....................................................................... 100
10.3.3.1 Jitter Buffer Status Registers (JB.) ........................................................................................ 104
10.3.3.2 Jitter Buffer Status Register Interrupt Enables (JB.) .............................................................. 107
10.3.4.1 Packet Classifier Configuration Registers (PC.) .................................................................... 110
10.3.4.2 Packet Classifier Status Register Latches (PC.) ................................................................... 113
10.3.4.3 Packet Classifier Status Register Interrupt Enables (PC.) ..................................................... 114
10.3.4.4 Packet Classifier Counter Registers (PC.) ............................................................................ 115
10.3.5.1 External Memory Interface Configuration Registers (EMI.) .................................................... 115
10.3.5.2 External Memory Interface Status Registers (EMI.)............................................................... 116
10.3.5.3 External Memory Interface Status Register Interrupt Enables (EMI.) ..................................... 117
10.3.5.4 External Memory DLL/PLL Test Registers (EMI.) .................................................................. 118
10.3.6.1 Write Registers (EMA.) ......................................................................................................... 118
10.3.6.2 Read Registers (EMA.) ........................................................................................................ 120
9.3.2.3.9
9.3.2.3.10 IP Packet with Unknown IP Destination Address (PC.CR6 – PC.CR16 and DPS1) ......... 60
9.3.2.3.11 “CPU Debug RXP PW Bundle” Setting (RXBDS) ............................................................ 61
9.3.2.3.12 PW Bundle with Unknown UDP Protocol Type (UPVCE and DPS5) ................................ 61
9.3.2.3.13 PW Bundle In-band VCCV OAM (RXOICWE and DPS7) ................................................ 61
9.3.2.3.14 PW Bundle with Too Many MPLS Labels (DPS10).......................................................... 61
9.3.2.3.15 PW OAM Bundle - Out-band VCCV OAM Packets (DPS7) ............................................. 61
9.3.3.1.1
TXP Packet Generation ................................................................................................................. 61
RXP CPU Packet Interface ............................................................................................................ 63
TXP CPU Packet Interface ............................................................................................................. 66
Global Resets ................................................................................................................................ 68
Latched Status and Counter Register Reset ................................................................................... 68
Buffer Manager .............................................................................................................................. 68
CPU Electrical Interconnect ........................................................................................................... 69
Interrupt Hierarchy ......................................................................................................................... 71
TXP SAT/CES/HDLC/Clock Only PW Packet Generation ....................................................... 62
TXP CPU Packet Generation ................................................................................................. 63
TXP Packet Scheduling .......................................................................................................... 63
TXP Packet Queue Monitoring ............................................................................................... 63
SDRAM Interface ................................................................................................................... 69
IP Packets with Unknown IP Protocol (DPS4) ................................................................. 60
L-bit Signaling ................................................................................................................ 63
DS34S132 DATA SHEET
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