DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 32

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

9.2 TDM Port Functions
The S132 includes 32 TDM Ports. Each TDM Port can be used to support a T1, E1 or any slower TDM data
stream. Each TDM Port uses a serial clock and data interface. The high level functions include:
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9.2.1 TDM Port Related Input and Output Clocks
The TDM Port Input and Output Clocks are identified in
Figure 9-7. TDM Port Input and Output Clock Overview
The S132 Clock Recovery Engines support “Adaptive Clock Recovery” (ACR) and “Differential Clock Recovery”
(DCR). The ACR technique measures the timing of each successive RXP Packet to determine the recovered clock
frequency. The DCR technique uses RTP timestamps to determine the recovered clock frequency. Two external
clock recovery reference inputs
input and 2) to provide a DCR common clock reference.
The Frequency Synthesizer reference input (synclk_ref_in) is required to generate an internal “synclk” signal. To
achieve the jitter/wander performance of ITU G.823/824/8261 the reference should be at least equal to that of a
Stratum 3 clock. The reference can be input on either
and Cellular Mobile Phone applications, the BITS or GPS Network Timing commonly provide at least a Stratum 3
reference. For applications where a Network Timing reference is not available, then an OCXO may be used. Some
specialized TCXOs can also meet these stringent requirements. Otherwise, if the jitter/wander requirements can be
relaxed then the synclk reference input signal requirements can be equally relaxed.
To support the DCR mode, both ends of the PW must share a common clock reference that is derived from a single
timing source so that the frequency of the common clock reference at both ends of the PW are locked to each
other. The
In public network applications that use the DCR mode, the public network broadcast Network Timing, that provides
a Stratum 3 or better reference (e.g. BITS or GPS), can be used for the DCR common clock (CMNCLK) input and
the synclk reference input; and the
In applications that use the DCR mode, but the DCR common clock reference is not a Stratum 3 reference (e.g.
private networks), the DCR common clock is connected to the
OCXO) is connected to the
In applications that do not use the DCR mode, only a high quality reference is required that can be connected to
CMNCLK
19-4750; Rev 1; 07/11
LIUCLK
EXTCLK0
EXTCLK1
RCLKn
TCLKOn
Structured & Unstructured Formats
T1, E1 and slower TDM Port Line Rates
T1SF, T1ESF and E1 Multi-frame Formats
N x 64 Kb/s PW Packet Payload Rates
With & without CAS Signaling
DS0 Timeslot Assignment
CPU Monitor and Control of CAS Signaling
or
CMNCLK
REFCLK
(n = 1 - 32)
Port n
TDM
LCE
input is used to provide the DCR common clock reference.
and the unused input pin can be tied low to save power.
Select
LCS
Ck
grclk
aclk_n
REFCLK
GRCSS
(REFCLK
1.544 MHz
2.048 MHz
REFCLK
32
32
input.
Recovery
and CMNCLK) are used to supply 1) a Frequency Synthesizer reference
32 Clock
Engines
input can be tied low to save power.
DS34S132
REFCLK
Figure
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9-7.
CPU Control for Data Conditioning
TDM Port Timing
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TDM Port, Timeslot and PW Loopbacks
BERT Diagnostics
or
CLAD
CMNCLK
CMNCLK
From Recovered or External Time References
Adaptive & Differential Clock Recovery
Generates Differential & Absolute Timestamps
_ref_in
synclk
Freq Select
input and a high quality reference (e.g.
(selected with G.CCR.SCS). For PSTN
FS[3:0]
Select
CLAD
Clock
SCS
DS34S132 DATA SHEET
CMNCLK
REFCLK
High Quality
Reference
(e.g. OCXO)
DCR
Common
Clock
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