DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 74

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

10
10.1 Register Block Address Ranges
Table 10-1. Register Block Address Ranges
19-4750; Rev 1; 07/11
Registers
Global Registers
Global Configuration Registers (G.)
Global Status Registers (G.)
Global Status Register Interrupt Enables (G.)
Individual Bundle and Jitter Buffer Registers
Global Bundle Reset Registers (B.)
Global Bundle Data Control Registers (B.)
Global Bundle Data Registers (B.)
Bundle Group Status Latch Registers (B.)
Bundle Group Status Register Interrupt Enables (B.)
Jitter Buffer Status Registers (JB.)
Jitter Buffer Status Register Interrupt Enables (JB.)
Packet Classifier Registers
Packet Classifier Configuration Registers (PC.)
Packet Classifier Status Register Latches (PC.)
Packet Classifier Status Register Interrupt Enables (PC.)
Packet Classifier Counter Registers (PC.)
SDRAM Interface and Access Registers
External Memory Interface Configuration Registers (EMI.)
External Memory Interface Status Registers (EMI.)
External Memory Interface Status Register Interrupt Enables (EMI.)
External Memory DLL/PLL Test Registers (EMI.)
Write Registers (EMA.)
Read Registers (EMA.)
Test, Diagnostics and Clock Registers
Encap BERT Registers (EB.)
Decap BERT Registers (DB.)
Miscellaneous Diagnostic Registers (MD.)
Test Registers (TST.)
Clock Recovery Registers (CR.)
Ethernet MAC Registers
MAC Registers (M.)
Per Port Registers
Port n TXP SW CAS Registers (TXSCn.; n = 0 to 31)
Port n Xmt (RXP) SW CAS Registers (RXSCn. ; n = 0 to 31)
Port n Transmit Configuration Registers (Pn.; n = 0 to 31)
Port n Transmit Status Registers (Pn.; n = 0 to 31)
Port n Transmit Status Register Latches (Pn.; n = 0 to 31)
Port n Transmit Status Register Interrupt Enables (Pn.; n = 0 to 31)
Port n Receive Configuration Registers (Pn.; n = 0 to 31)
Port n Receive Status Registers (Pn.; n = 0 to 31)
Port n Receive Status Register Latches (Pn.; n = 0 to 31)
Port n Receive Status Register Interrupt Enables (Pn.; n = 0 to 31)
Time Slot Assignment Registers (TSAn.m.; n = 0 – 31; m = 0 – 31)
DEVICE REGISTERS
Address Range
03C0h – 03DFh
0C00h – 0DBFh
00A4h – 00EFh
03A0h – 03AFh
03B0h – 03B7h
03B8h – 03BFh
03E0h – 03FFh
0480h – 04AFh
0800h – 0BFFh
2000h – 2FFFh
0000h – 002Fh
0030h – 005Fh
0060h – 007Fh
0080h – 008Fh
0094h – 00A3h
0100h – 017Fh
0180h – 01FFh
0200h – 027Fh
0280h – 02FFh
0300h – 035Fh
0368h – 036Fh
0370h – 037Fh
0380h – 039Fh
0400h – 043Fh
0440h – 047Fh
0600h – 067Fh
1000h – 11FFh
1200h – 13FFh
0360h – 0367h
3000h – 4000h
DS34S132 DATA SHEET
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