DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 43

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

a Bundle is equivalent to enabling a “Connection” for that Engine (e.g. enabling SAT/CES Engine = enable
SAT/CES Connection).
forward the packets for a Bundle to the CPU (for debug; CPU Debug RXP PW Bundle) or to discard the packet
payload for Clock Only Bundles (to reduce the S132 payload processing functions). The following types of Bundles
can be programmed using these registers. The “Register Definition” and the “Register Guide” sections provide
more information on how to set these registers for each Bundle type.
The SAT and CES Bundles can include an RXP PW-Timing Connection by enabling
PW-Timing Connection by including the RTP Timestamp in the TXP Header Descriptor for that Bundle (see the
“TXP SAT/CES and HDLC PW Packet Generation” section). The Clock Recovery functions are described in more
detail in the “PW-Timing” section.
All of the Bundle types can include support for In-band VCCV (In-band VCCV CPU Connection). When a packet is
received for a recognized Bundle, the received packet header matches the In-band VCCV Control Word
(PC.CR5.VOV
B.BCDR4.RXOICWE) the S132 forwards the In-band VCCV packet to the CPU or discards the packet according to
the
In the TXP direction, Receive TDM Port data that is ready for transmission is buffered in one of two priority queues
so that the packets can be scheduled according to their importance when congestion occurs. TXP Packets that are
buffered in the higher priority queue are processed before TXP Packets in the lower priority queue. For example,
Bundles with PW-Timing Connections can be assigned to the higher priority queue. The TXP priority is selected for
each TXP Bundle using B.BCDR3.TXBPS.
9.2.5.1
The S132 includes 256 HDLC Engines, one each for up to 256 Bundles. Several HDLC Bundle types are supported
including Unstructured HDLC (full TDM Port bandwidth), Structured Nx64 Kb/s HDLC, Structured 56 Kb/s or
Structured 16 Kb/s. With HDLC Bundles the terms “Unstructured” and “Structured” refer to the format of the TDM
Port. These terms do not have any direct relevance to the packet format of an HDLC Bundle. A single Structured
TDM Port can support any combination of Structured HDLC Bundles and CES Bundles since each Bundle can be
assigned to independent Timeslots on a Structured TDM Port.
Figure 9-14. HDLC Engine Environment
An Unstructured HDLC Bundle uses the entire bandwidth of its assigned TDM Port. The HDLC coding/decoding is
performed using the entire data stream without regard for T1/E1 framing or Timeslot positions.
Structured HDLC Bundles can be programmed to use 2-bit, 7-bit or 8-bit HDLC coding (for 16 Kb/s, 56 Kb/s and
“Nx64 Kb/s” channels respectively; B.BCDR1.SCTXCOS). The bit-width setting identifies how many bits are used in
the assigned Timeslot. For 8-bit, all 8 bits of the timeslot are HDLC coded. For 7-bit coding, only the 7 MSbits are
HDLC coded (the LSbit is unused). For 2-bit coding, the two MSbits or two LSbits can be selected for HDLC coding
(the remaining 6-bits are unused). Unstructured HDLC Bundles always use 8-bit coding.
The “8-bit” format allows an HDLC Bundle to combine the data from multiple 8-bit Timeslots of a single Structured
T1/E1 to support bandwidths like 384 Kb/s (using six 8-bit Timeslots). Any number of 8-bit Timeslots can be
combined (up to 24 for Structured T1 or 31 for Structured E1).
Only one 2-bit or 7-bit HDLC coded Timeslot from a Structured T1/E1 can be assigned to an HDLC Bundle.
19-4750; Rev 1; 07/11
DS34S132
SAT
Nx64 CES without CAS
Nx64 CES with CAS
PC.CR1.DPS7
RXP
TXP
TSA
TSA
HDLC Engine
and PC.CR5.VOM) and In-band VCCV has been enabled for that Bundle
setting (OAM Packet Discard switch; this switch also affects other OAM types).
B.BCDR1.RXBDS
RXP HDLC Engine
TXP HDLC Engine
HDLC for Unstructured TDM Port
Structured Nx64 HDLC
Structured 56 Kb/s or 16 Kb/s HDLC
further supplements these selections by providing the ability to instead
Connection
HDLC
Manager
Buffer
SAT Clock Only
CES Clock Only
B.BCDR4.PCRE
DS34S132 DATA SHEET
(B.BCDR4.RXCWE
and/or a TXP
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