DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 107

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

10.3.3.2 Jitter Buffer Status Register Interrupt Enables (JB.)
Table 10-12. Jitter Buffer Status Register Interrupt Enables (JB.)
19-4750; Rev 1; 07/11
JB. Field
Name
G0SRIE.
RSVD
JBUIE
[7:0]
G1SRIE.
RSVD
JBUIE
[15:8]
G2SRIE.
RSVD
JBUIE
[23:16]
G3SRIE.
RSVD
JBUIE
[31:24]
G4SRIE.
RSVD
JBUIE
[39:32]
G5SRIE.
RSVD
JBUIE
[47:40]
G6SRIE.
RSVD
JBUIE
[55:48]
G7SRIE.
RSVD
JBUIE
[63:56]
G8SRIE.
RSVD
JBUIE
[71:64]
G9SRIE.
RSVD
JBUIE
[79:72]
Addr (A:)
Bit [x:y]
A:0280h
A:0284h
A:0288h
A:028Ch
A:0290h
A:0294h
A:0298h
A:029Ch
A:02A0h
A:02A4h
[31:8]
[31:8]
[31:8]
[31:8]
[31:8]
[31:8]
[31:8]
[31:8]
[31:8]
[31:8]
[7:0] rwc-_-i3
[7:0] rwc-_-i3
[7:0] rwc-_-i3
[7:0] rwc-_-i3
[7:0] rwc-_-i3
[7:0] rwc-_-i3
[7:0] rwc-_-i3
[7:0] rwc-_-i3
[7:0] rwc-_-i3
[7:0] rwc-_-i3
Type
Description
Group 0 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
G0SRL[z] = 1 and G0SRIE[z] = 1, forces G.GSR6[0] = 1.
Group 1 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G1SRL[z] = 1 and JB.G1SRIE[z] = 1, forces G.GSR6[1] = 1.
Group 2 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G2SRL[z] = 1 and JB.G2SRIE[z] = 1, forces G.GSR6[2] = 1.
Group 3 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G3SRL[z] = 1 and JB.G3SRIE[z] = 1, forces G.GSR6[3] = 1.
Group 4 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G4SRL[z] = 1 and JB.G4SRIE[z] = 1, forces G.GSR6[4] = 1.
Group 5 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G5SRL[z] = 1 and JB.G5SRIE[z] = 1, forces G.GSR6[5] = 1.
Group 6 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G6SRL[z] = 1 and JB.G6SRIE[z] = 1, forces G.GSR6[6] = 1.
Group 7 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G7SRL[z] = 1 and JB.G7SRIE[z] = 1, forces G.GSR6[7] = 1.
Group 8 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G8SRL[z] = 1 and JB.G8SRIE[z] = 1, forces G.GSR6[8] = 1.
Group 9 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G9SRL[z] = 1 and JB.G9SRIE[z] = 1, forces G.GSR6[9] = 1.
DS34S132 DATA SHEET
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