DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 118

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

10.3.5.4 External Memory DLL/PLL Test Registers (EMI.)
Table 10-20. External Memory DLL/PLL Test Registers (EMI.)
10.3.6 External Memory Access Registers (EMA.)
10.3.6.1 Write Registers (EMA.)
Table 10-21. Write Registers (EMA.)
19-4750; Rev 1; 07/11
EMI. Field
Name
RPI1WER
RSL
RPI2WER
RSL
TDI1ERR
SL
TDI2ERR
SL
TEI1ERR
SL
TEI2ERR
SL
TPI1ERR
SL
TPI2ERR
SL
EMI. Field
Name
TCR1.
PTR
DTR
TCR2.
RSVD
PPCR
DPCR
EMA. Field
Name
WCR.
RSVD
TLBE
Addr (A:)
Bit [x:y]
Addr (A:)
Bit [x:y]
A:03B8h
A:03BCh
Addr (A:)
Bit [x:y]
A:03C0h
[31:16] rwc-_-_
[15:0] rwc-_-_
[31:9]
[31:17]
[16:13] rwc-_-_
[8:7] rwc-_-_
[6:0] rwc-_-_
[7] rls-crw-_
[6] rls-crw-_
[5] rls-crw-_
[4] rls-crw-_
[3] rls-crw-_
[2] rls-crw-_
[1] rls-crw-_
[0] rls-crw-_
Type
Type
Type
Description
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Description
Test Configuration Register 1. Default: 0x00.00.00.00
Reserved.
Reserved.
Test Configuration Register 2. Default: 0x00.00.00.00
Reserved.
Reserved.
Reserved.
Description
Write Control Register. Default: 0x00.00.00.00
Reserved.
Transfer Last Byte Enable is used to indicate to the S132 which bytes are valid
in the last double-word stored in the TXP CPU FIFO (each bit enables 1 of 4
bytes). This function is used when TPCWC = 6 and a complete TXP CPU packet
has already been stored at EMA.WDR.EMWD. TLBE = 0x1 = “1 byte in the least
significant byte position”. TLBE = 0xF = “4 bytes”.
DS34S132 DATA SHEET
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