DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 23

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

19-4750; Rev1; 7/11
Pin Name
RXD[7:0]
RXDV
RXER
COL
CRS
MDC
MDIO
CPU Interface
PD[31:0]
PA[13:2]
PA[1]
PALE
PCS_N
PRW
Type
Oz
IO
IO
I
I
I
I
I
I
I
I
I
I
Pin Description
Receive Data 0 through 7(GMII Mode – RXD[0:7]). Eight bits of received data,
sampled synchronously with the rising edge of RXCLK. For every clock cycle, the
PHY transfers 8 bits to the device. RXD[0] is the least significant bit of the data. Data
is not considered valid when RXDV is low.
Receive Data 0 through 3(MII Mode – RXD[0:3]). Four bits of received data,
sampled synchronously with RXCLK. Accepted when CRS is asserted. When MII
mode is selected, RXD[4:7] pins are not used.
Receive Data Valid (GMII). This active high signal, synchronous to RXCLK, indicates
valid data from the PHY. In GMII mode the data RXD[0:7] is ignored if RXDV is not
asserted high.
Receive Data Valid (MII). This active high signal, synchronous to RXCLK, indicates
valid data from the PHY. In MII mode the data RXD[0:3] is ignored if RXDV is not
asserted high.
Receive Error (GMII). This signal indicates a receive error or a carrier extension in
the GMII Mode.
Receive Error (MII). Asserted by the PHY for one or more RXCLK periods indicating
that an error has occurred. Active high indicates receive packet is invalid.
MII and GMII modes: This is synchronous with RXCLK.
Collision Detect (MII). Asserted by the Ethernet PHY to indicate that a collision is
occurring. This signal is only valid in half duplex mode, and is ignored in full duplex
mode.
Receive Carrier Sense. This signal is asserted by the PHY when either transmit or
receive medium is active. This signal is not synchronous to any of the clocks.
Management Data Clock. A divided down SYSCLK that clocks management data to
and from the PHY.
Management Data IO. Data path for control information between the device and the
PHY. Pull to logic high externally through a 1.5K ohm resistor. The MDC and MDIO
pins are used to write or read up to 32 Control and Status Registers in PHY
Controllers. This port can also be used to initiate Auto-Negotiation for the PHY.
32-bit Processor Data Bus. PD[31] is the MSB which should be mapped to D[0] of a
MPC8xxx processor.
16-bit Processor Data Bus. PD[15] is the MSB which should be mapped to D[0] of a
MPC8xxx processor. PD[31:16] is not used and should be tied low.
32-bit & 16-bit Processor Data Bus. Input signals on this bus are captured by the
rising edge of SYSCLK. Output signals are updated on the rising edge of SYSCLK.
Processor Address Bus. The signals on this bus are captured by the rising edge of
SYSCLK.
32-bit Processor Address Bus Bit 1. PA[1] is not used and should be tied low.
32-bit Processor Address Bus Bit 1. When PA[1] = 0, PD[15:0] carries the upper 16
bits of the 32-bit word. When PA[1] = 1, PD[15:0] carries the lower 16 bits of the 32-bit
word.
Processor Address Latch. PALE latches PA[13:1] on its falling edge. In non-muxed
mode, tie high.
Processor Chip Select. Processor chip select active low. Synchronous to SYSCLK.
Processor Read/Write. The behavior of this signal is described by PRWCTRL. This
signal is synchronous to SYSCLK.
DS34S132 DATA SHEET
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