DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 69

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

9.6.3.1
The S132 has been designed to work with DDR-SDRAM devices that are compatible with the JEDEC JESD79C
standard and that support 2-2-2 timing with a clock rate of at least 125 MHz.
device sizes that can be used to support different Jitter Buffer Depth/Bundle Count combinations.
Table 9-17. SDRAM Device Selection Table
Note:
The external SDRAM is used by many of the S132 processes so the SDRAM interface should be configured before
any of the TDM or Ethernet Ports are enabled. The SDRAM column width, memory size and control functions must
be programmed
used to reset the SDRAM after changing the
The SDRAM clock must be 125 MHz and can be derived from the
9.6.4 CPU Electrical Interconnect
The CPU interface is used to program the S132, to transmit and receive CPU Packets (to/from the Ethernet Port)
and to monitor the various status and interrupt signals from the S132. The CPU interface supports two processor
interface types, one to work with processors like the Freescale MPC870 (depicted in
work with processors like the Freescale MPC8313 (depicted in
processor supports a non-multiplexed and multiplexed mode, which determines whether the S132 PA[13:10]
signals are connected to the processor address or data bus.
19-4750; Rev 1; 07/11
Single SDRAM Device Description
512 Mb
512 Mb
256 Mb
128 Mb
Array
Size
1
These SDRAM vendor parts are targeted for use with the S132. Compatibility with these parts has not yet been fully
verified.
SDRAM Interface
Width
16 bit
16 bit
16 bit
16 bit
Data
(EMI.DCR2
Targeted Vendor Part #
Micron MT46V32M16P-6T or
Samsung K4H511638B-TCB3
Micron MT46V32M16P-6T or
Samsung K4H511638B-TCB3
Micron MT46V16M16P-75E
Micron MT46V8M16P-75E
and
EMI.DCR3)
EMI.DCR2
1
to match to the DDR SDRAM that is used.
Qty SDRAM
Devices per
DS34S132
and
2
1
1
1
EMI.DCR3
Figure 9-30
ETHCLK
Total SDRAM
bits per
DS34S132
1 Gbit
512 Mbit
256 Mbit
128 Mbit
settings.
or
and
Table 9-17
DDRCLK
Figure
Figure
Max Configurable Values
Bundle
Count
(G.GCR.ECDC).
9-31). The MPC8313 style
DS34S132 DATA SHEET
256
128
256
128
256
128
256
EMI.DCR1.DIR
identifies several SDRAM
64
32
64
9-29) and the other to
Depth (JBMD)
Jitter Buffer
256 Kbyte
256 Kbyte
128 Kbyte
256 Kbyte
128 Kbyte
256 Kbyte
128 Kbyte
64 Kbyte
64 Kbyte
32 Kbyte
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should be