DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 80

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

Register Name
TSTCR
Miscellaneous Diagnostic Registers (MD.)
DCR
EBCR
DBCR
MBSR1
MBSR2
MBSR3
MBSR4
MBSR5
Test Registers (TST.)
GTR1
BTCR1
BTCR2
BTCR3
BTCR4
BTCR5
BTCR6
CRJBT
BTSR1
BTSR2
BTSR3
BTSR4
BTSR5
BTSR6
CTCR1
CTCR2
CTCR3
CTCR4
EDTCR
EDTSR1
EDTSR2
EDTSR3
EDTSR4
EDTSR5
FID
Clock Recovery Registers (CR.)
CRCR
MAC Registers (M.)
NET_CONTROL.
NET_CONFIG
NET_STATUS
RSVD
USER_IO
TX_STATUS
RX_QPTR
TX_QPTR
RX_STATUS
IRQ_STATUS
IRQ_ENABLE
IRQ_DISABLE
IRQ_MASK
PHY_MAN
RX_PAUSE_TIME
TX_PAUSE_QUANT
19-4750; Rev 1; 07/11
Addr (hex)
0C0C
0C1C
0C2C
0C3C
04AC
060C
061C
062C
064C
066C
06FC
0C00
0C04
0C08
0C10
0C14
0C18
0C20
0C24
0C28
0C30
0C34
0C38
04A0
04A4
04A8
04B0
0470
0480
0484
0488
0600
0604
0608
0610
0614
0618
0624
0628
0630
0634
0638
0640
0644
0648
0660
0664
0668
0670
0674
0800
Description
Test Control Register
Diagnostic Control Register
Encap BERT Control Register
Decap BERT Control Register
Memory BIST Status Register 1
Memory BIST Status Register 2
Memory BIST Status Register 3
Memory BIST Status Register 4
Memory BIST Status Register 5
Global Test Control Register 1
Block Test Control Register 1
Block Test Control Register 2
Block Test Control Register 3
Block Test Control Register 4
Block Test Control Register 5
Block Test Control Register 6
Clock Recovery Jitter Buffer Test
Block Test Status Register 1
Block Test Status Register 2
Block Test Status Register 3
Block Test Status Register 4
Block Test Status Register 5
Block Test Status Register 6
CLAD Test Control Register 1
CLAD Test Control Register 2
CLAD Test Control Register 3
CLAD Test Control Register 4
Encap/Decap Test Control Register
Encap/Decap Test Status Register 1
Encap/Decap Test Status Register 2
Encap/Decap Test Status Register 3
Encap/Decap Test Status Register 4
Encap/Decap Test Status Register 5
Block Test Control Register 6
Clock Recovery Control Register
Network Control Register
Network Configuration Register
Network Status Register
Reserved
User Input/Output Register
Transmit Status Register
Receive Buffer Queue Base Address
Transmit Queue Base Address
Receive Status Register
Interrupt Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Phy Maintenance Register
Received Pause Quantum Register
Transmit Pause Quantum Register
DS34S132 DATA SHEET
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