DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 117

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

10.3.5.3 External Memory Interface Status Register Interrupt Enables (EMI.)
Table 10-19. External Memory Interface Status Register Interrupt Enables (EMI.)
19-4750; Rev 1; 07/11
EMI. Field
Name
ETRCSL
ETWCSL
TXPSRCS
L
TXPSWC
SL
TXHSRCS
L
EMI. Field
Name
BMSRIE.
RSVD
CERCIE
CEWCIE
ECRCIE
ECWCIE
ETRCIE
ETWCIE
TXPSRCI
E
TXPSWCI
E
TXHSRCI
E
TSRL
RSVD
EMARER
RSL
EMAWER
RSL
RPIRERR
SL
Addr (A:)
Bit [x:y]
Addr (A:)
Bit [x:y]
A:03B0h
A:03B4h
[31:11]
[31:9]
[10] rls-crw-_
[4] rls-crw-i3
[3] rls-crw-i3
[2] rls-crw-i3
[1] rls-crw-i3
[0] rls-crw-i3
[8] rwc-_-i3
[7] rwc-_-i3
[6] rwc-_-i3
[5] rwc-_-i3
[4] rwc-_-i3
[3] rwc-_-i3
[2] rwc-_-i3
[1] rwc-_-i3
[0] rwc-_-i3
[9] rls-crw-_
[8] rls-crw-_
Type
Type
Description
Ethernet to TDM Read Check Status Latch = “1” indicates one or more SDRAM
Read operations were invalid due to EMI.BMCR2.JBSO. The Jitter Buffer Queues
overlap with another SDRAM queue due to an invalid EMI Start Address setting.
The combination of ETRCSL = 1 and ETRCIE = 1 forces G.GSR1.EMIS = 1.
Ethernet to TDM Write Check Status Latch = “1” indicates 1 or more SDRAM
Write operations were invalid due to EMI.BMCR2.JBSO. The Jitter Buffer Queues
overlap with another SDRAM queue due to an invalid EMI Start Address setting.
The combination of ETWCSL = 1 and ETWCIE = 1 forces G.GSR1.EMIS = 1.
TXP Packet Space Read Check Status Latch = “1” indicates 1 or more SDRAM
Read operations were invalid due to EMI.BMCR1.TXPSO. The TXP TDM Packet
Queues overlap with another queue due to an invalid EMI Start Address. The
combination of TXPSRCSL = 1 and TXPSRCIE = 1 forces G.GSR1.EMIS = 1.
TXP Packet Space Write Check Status Latch = “1” indicates 1 or more SDRAM
Write operations were invalid due to EMI.BMCR1.TXPSO. The TXP TDM Packet
Queues overlap with another queue due to an invalid EMI Start Address. The
combination of TXPSWCSL = 1 and TXPSWCIE = 1 forces G.GSR1.EMIS = 1.
TXP Header Space Read Check Status Latch = “1” indicates 1 or more SDRAM
Read operations were invalid due to EMI.BMCR1.TXHSO. The TXP TDM Header
space overlaps with another queue due to an invalid EMI Start Address. The
combination of TXHSRCSL = 1 and TXHSRCIE = 1 forces G.GSR1.EMIS = 1.
Description
Buffer Manager Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
CPU to Ethernet Read Check Interrupt Enable. (see EMI.BMSRL.CERCSL)
CPU to Ethernet Write Check Interrupt Enable. (see EMI.BMSRL.CEWCSL)
Ethernet to CPU Read Check Interrupt Enable. (see EMI.BMSRL.ECRCSL)
Ethernet to CPU Write Check Interrupt Enable. (see EMI.BMSRL.ECWCSL)
Ethernet to TDM Read Check Interrupt Enable. (see EMI.BMSRL.ETRCSL)
Ethernet to TDM Write Check Interrupt Enable. (see EMI.BMSRL.ETWCSL)
TXP Packet Space Read Check Interrupt Enable. (see EMI.BMSRL.TXPSRSL)
TXP Packet Space Write Check Interrupt Enable. (see
EMI.BMSRL.TXPSWCSL)
TXP Header Space Read Check Interrupt Enable. (see
EMI.BMSRL.TXHSRCSL)
Test Status Register Latched
Reserved.
Reserved.
Reserved.
Reserved.
DS34S132 DATA SHEET
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