DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 145

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

19-4750; Rev 1; 07/11
Pn. Field
Name
DBVSE
LB
LBSS
SPL
RSVD
PRCR2.
RSVD
RSTS
RDS
RSVD
RIES
RSVD
RSS
PRCR3.
PTPRTSL
PRCR4.
RSVD
TSGMS
TSGMC
PRCR5.
RSVD
TSGN1C
Addr (A:)
Bit [x:y]
A:2044h
A:2048h
A:204Ch
A:2050h
[31:17]
[31:29]
[28:16] rwc-_-_
[11:1] rwc-_-_
[31:7]
[31:0] rwc-_-_
[15:0] rwc-_-_
[2:1]
[14] rwc-_-_
[13] rwc-_-_
[12] rwc-_-_
[16] rwc-_-_
[0]
[6] rwc-_-_
[5] rwc-_-_
[4]
[3] rwc-_-_
[0] rwc-_-_
Type
Description
D Bit Value for SF to ESF. Sets the value of the D bit when mapping SF locally
to ESF at the destination.
L Bit. This sets the L bit value for all Bundles sourced by this port.
L Bit Source Select selects the L-bit source for all TXP Bundles for this T1/E1
port: 0 = PRCR1.LB value or 1 = L-bit programmed in each TXP Bundle header.
SAT Payload Length. Set to the # bytes per packet payload (SAT mode only).
SPL must = PMS and must be ≥ BPF. For example for T1 SAT, SPL = PMS =
0x17 (for 24 timeslots) and BPF must be set to 0x17 or less.
Reserved.
Port Receive Configuration Register 2. Default: 00.00.00.08h
Reserved.
Receive Frame Synchronization .
RSYNC Direction Select. This bit selects the direction of the RSYNC signal.
Reserved.
Receive Input Edge Select. This bit selects the edge to be used for port receive
data capture on inputs relative to RCLK.
Reserved.
RCLK Source Select. This bit is used to select the source of the clock used to
time the port receive interface. This selects the source clock for capture of RDAT,
RSIG, and RSYNC.
Port Receive Configuration Register 3. Default: 0x00.00.00.00
PT to PR Time Slot Loopback. Each bit selects the TDM loopback for the
corresponding time slot from the port transmit to the port receive; bit 0 enables
port loop back for time slot 0, bit 1 enables port loop back for time slot 1, etc. You
may use either the loopback for PR to PT or PT to PR, but not both at the same
time; i.e. the control for the unused direction must not have any timeslots selected
for loopback. Note that for T1, bits 31:24 are not used.
Port Receive Configuration Register 4. Default: 0x00.00.00.00
Reserved.
RTP Time Stamp Generator Mode Select.
Timestamp Generator M Coefficient is defined by the following equation where
TSPCLK = “remote PW Timestamp clock rate” (TSPCLK and CMNCLK are
specified in bits/sec; only valid for TSGMS = 0). In most applications TSPCLK =
CMNCLK and TSGMC = 4096 decimal = 0x1000.
Port Receive Configuration Register 5. Default: 0x00.00.00.00
Reserved.
Timestamp Generator N1 Coefficient is defined by the following equation (see
TSGMC). In most applications TSPCLK = CMNCLK and TSGN1C = 0x0000.
1 = synchronized to internal TDM Port Transmit frame timing (system timing)
1 = output
1 = negative edge
1 = TCLKO Signal output
1 = derived from RSS selected receive TDM Port timing (Absolute Timestamp)
0 = synchronized to RSYNC signal input
0 = input
0 = positive edge
0 = RCLK Signal input
0 = derived from CMNCLK (Differential Timestamp)
TSGMC = Integer [4096 * (TSPCLK ÷ CMNCLK)]
TSGN1C = (CMNCLK ÷ 8000) * [TSGMC – 4096 * (TSPCLK ÷ CMNCLK)]
DS34S132 DATA SHEET
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