DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 168

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DS34S132GNA2+

Manufacturer Part Number
DS34S132GNA2+
Description
Communication ICs - Various 32Port TDM-Over-Pack Transport Device
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS34S132GNA2+

Rohs
yes
Part # Aliases
90-34S13+2N2
10.4.5.2 Global Packet Classifier Monitoring Control
Table 10-65. Global Packet Classifier Monitoring Settings (PC.)
Register
CPCR.CPC
PCECR.UICPEC
CR1.UICECS
SPCR.SPC
10.4.5.3 Global RXP Bundle Monitoring Control
Table 10-66. Global RXP Bundle Control Word Change Monitor Settings(G.)
Register
GCR.LBCDE
GCR.RBCDE
GCR.MBCDE
GCR.FBCDE
Notes:
10.4.5.4 Global TXP Packet Queue Monitoring
Table 10-67. Global TXP Output Queue Status Registers (G.)
Status Register
TPISR1.TXHPQML
TPISR2.TXLPQML
TPISR3.TXCQML
Notes:
10.4.5.5 PW Bundle Monitoring
Table 10-68. TXP Bundle Status/Statistics Registers
Bundle/Port
Select
B.BESCR
Pn.
19-4750; Rev 1; 07/11
1
1
When an intended SAT/CES Bundle is programmed to be sent to the CPU the Control Word Change Detect bits can
be monitored for debug purposes (this is not a normal CPU Bundle function).
High priority normally is only assigned to SAT/CES/Clock Only Bundles used for Clock Recovery at PW far end.
Status
Register
BESR1
BESR2
BESR3
PTSR1-4
Control Word Function
L-bit Change Detect Enable
R-bit Change Detect Enable
M-bit Change Detect Enable
Frag-bit Change Detect Enable
Packet Classifier Function
Good Packet Count
UDP & IP Pkt FCS Error Count
UDP & IP FCS Error Select
Stray Packet Count
Functional Description
TXP High Priority Queue Max Level
TXP Low Priority Queue Max Level
TXP CPU Queue Max Level
Status
Bits
PRHEFC
GPTXC
TXPSFSL
CTSx
Functional Description
Bad Rcv HDLC Frame Count
Good TXP Packet (Ethernet) Count
TXP Queue Overflow
TXP CAS in Time Slot x
Description
# received packets forwarded toward a TDM Port or CPU
# received packets with UDP & IP checksum errors (see UICECS)
Selects whether UICPEC counts UDP, IP or “UDP and IP” checksum errors
# received packets with PW header, but unknown PWID (no BID or OAM BID match)
SAT/CES
Bundle
Yes
Yes
Yes
Yes
1
SAT/CES
Bundle
Yes
Yes
NA
SAT
Bundle
Yes
Yes
Yes
NA
HDLC Bundle
NA
NA
NA
NA
HDLC
Bundle
Yes
Yes
NA
SAT/CES
Bundle
NA
Yes
Yes
Yes
HDLC
Bundles
Yes
Yes
Yes
NA
Clock-only
Bundle
Yes
Yes
NA
Clock-only
Bundle
NA
Yes
Yes
NA
DS34S132 DATA SHEET
Clock-only
Bundles
NA
Yes
Yes
NA
All CPU connection
types
NA
NA
Yes
CPU Debug
Bundle
Yes
Yes
Yes
Yes
CPU Debug
Bundles
NA
NA
NA
NA
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