DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 35
DS34S132GNA2+
Manufacturer Part Number
DS34S132GNA2+
Description
Communication ICs - Various 32Port TDM-Over-Pack Transport Device
Manufacturer
Maxim Integrated
Datasheet
1.DS34S132GNA2.pdf
(194 pages)
Specifications of DS34S132GNA2+
Rohs
yes
Part # Aliases
90-34S13+2N2
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9.2.1.2
Each TDM Port can be independently programmed to support “One Clock” or “Two Clock” operation. In the “One
Clock” mode, the transmit and receive directions are both timed relative to either
line rates that are synchronized to a local system clock (System Timed) or relative to
programmed to be “Loop Timed”.
In the “Two Clock” mode
line rates and/or clock phases of the TXP and RXP directions to be different. This supports the most generalized
case for asynchronous transmit and receive timing.
Table 9-1. One-Clock and Two-Clock Mode settings
Mode
One Clock Mode using
One Clock Mode using
Two Clock Mode (independent receive and transmit timing)
9.2.2 TDM Port Interface
Each TDM Port supports independent transmit and receive NRZ data, clock, sync pulse and signaling pins.
9-10
Figure 9-10. TDM Port #1 Environment
When configured for Structured (CES), the
synchronization, CAS and Timeslot positions. For Unstructured (SAT), the
and the entire TDM Port bandwidth is transported in the TDM-over-Packet payload without regard to framing.
The TSYNC and RSYNC signals can be programmed to be input or output signals, although they are portrayed in
this diagram as unidirectional.
19-4750; Rev 1; 07/11
Framer
T1/E1
LIU &
provides a high level view of the interconnections to TDM Port “n”.
TDM Port - One Clock and Two Clock Modes
TSYNCn, TCLKOn
RSYNCn, RCLKn
RDATn, RSIGn,
TDATn, TSIGn,
TCLKO
RCLKn
RCLK
RCLK
TCLKOn
(Loop Timed)
Figure 9-11
(System Timed)
is used to time receive data and
TDM Rcv
TDM Xmt
Port n
Port n
TCLKOn
provides a more detailed view of the TDM Port Interface.
RSYNCn/TSYNCn
RCLKn
Table 9-1
RXP
TXP
TSA
TSA
grclk
identifies how to select between these modes.
aclk_n
TCLKO
Global Clock Recovery Select
Pn.PTCR2.TSS
signals are used to identify the T1/E1 frame
1, 2, 4 or 5
1, 2, 4 or 5
is used to time transmit data allowing the
0
Port 0 Ck Recov Engine
RSYNCn/TSYNCn
Recovery Engine
Port 31 Ck Recov Engine
Port n Clock
TCLKOn
RCLKn
DS34S132 DATA SHEET
DS34S132
for TDM Ports that have
for TDM Ports that are
Pn.PRCR2.RSS
signals are ignored
0
1
0
35 of 194
EXTCLK0
EXTCLK1
Figure
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