DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 115

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

10.3.4.4 Packet Classifier Counter Registers (PC.)
Table 10-16. Packet Classifier Counter Registers (PC.)
10.3.5 External Memory Interface Registers (EMI.)
10.3.5.1 External Memory Interface Configuration Registers (EMI.)
Table 10-17. External Memory Interface Configuration Registers (EMI.)
19-4750; Rev 1; 07/11
PC. Field
Name
CPCR.
CPC
PCECR.
RSVD
UICPEC
SPCR.
SPC
FOCR.
RSVD
FOC
EMI. Field
Name
BMCR1.
TXPSO
TXHSO
BMCR2.
RSVD
JBSO
BMCR3.
PTSO
PRSO
DCR1.
RSVD
DIR
Addr (A:)
Bit [x:y]
A:0370h
A:0374h
A:0378h
A:037Ch
Addr (A:)
Bit [x:y]
A:0380h
A:0384h
A:0388h
A:0390h
[31:16]
[31:16]
[31:16] rwc-_-_
[31:16]
[31:16] rwc-_-_
[31:0] rcs-cor-nc
[15:0] rcs-cor-nc
[31:0]
[15:0]
[15:0] rwc-_-_
[15:0] rwc-_-_
[15:0] rwc-_-_
[31:1]
[0] rwc-_-_
Type
Type
Description
Classified Packet Counter Register. Default: 0x00.00.00.00
Classified Packet Count indicates # of “good” RXP packets that have been
forwarded to a CES/SAT Engine, Clock Recovery Engine or the CPU Queue.
IP/UDP Packet Checksum Error Counter Register. Default: 0x00.00.00.00
Reserved.
UDP IP Checksum Packet Error Count indicates the # of received IPv4 or UDP
checksum errors (error type selected using PC.PCECR.UICPEC).
Stray Packet Count Register. Default: 0x00.00.00.00
Stray Packet Count indicates the # of received packets that include a PW
Header but do not match any of the configured Bundle IDs or OAM Bundle IDs.
FIFO Overflow Counter Register. Default: 0x00.00.00.00
Reserved.
Reserved.
Description
Buffer Manager Configuration Register 1. Default: 0x00.00.00.00
TXP Packet Space Offset specifies the starting address in the external SDRAM
for storing TXP TDM payload (the location where Bundle 0 payload is stored).
TXP Header Space Offset specifies the starting address in the external SDRAM
for storing TXP TDM Headers (the location where the Bundle 0 Header is stored).
Buffer Manager Configuration Register 2. Default: 0x00.00.00.00
Reserved.
Jitter Buffer Space Offset specifies the starting address in the external SDRAM
for storing RXP TDM packets (the location where Bundle 0 packets are stored).
Buffer Manager Configuration Register 3. Default: 0x00.00.00.00
Packet Transmit Space Offset specifies the starting address in the external
SDRAM for storing TXP CPU packets.
Packet Receive Space Offset specifies the starting address in the external
SDRAM for storing RXP CPU packets.
DDR SDRAM Configuration Register 1. Default: 0x00.00.00.00
Reserved.
DDR SDRAM Initialization Reset re-initializes the EMI.DCR3.DBMR and
EMI.DCR3.DEMR register bits when DIR transitions from zero to one.
TXP TDM payload starting address = 2048 bytes * TXPSO
TXP TDM Header starting address = 2048 bytes * TXHSO
RXP TDM packet starting address = 2048 bytes * JBSO
TXP CPU packet starting address = 2048 bytes * PTSO
RXP CPU packet starting address = 2048 bytes * PRSO
DS34S132 DATA SHEET
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