DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 121

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

19-4750; Rev 1; 07/11
EMA. Field
Name
RSVD
RSR2.
RSVD
RQL
RSVD
RQRP
RFL
RSRL1.
RSVD
RPNRSL
RQOSL
RQNESL
RSVD
RFUSL
RFRSL
RTOSL
RSVD
RSRIE1.
RSVD
RPNRIE
RQOIE
RQNEIE
RSVD
RFUIE
RFRIE
RTOIE
RSVD
Addr (A:)
Bit [x:y]
A:03F0h
A:03F4h
A:03F8h
[30:21] ros-_-_
[20:19]
[18:10] ros-_-_
[31:19]
[31:19]
[15:8]
[15:8]
[5:0]
[9:0] ros-_-_
[4:0]
[4:0]
[31]
[18] rls-crw-i3 Read Preempted by New Request Status Latch = “1” indicates one or more
[17] rls-crw-i3 Read Queue Overflow Status Latch = “1” = SDRAM RXP CPU Queue
[16] rls-crw-i3 Read Queue Not Empty Status Latch = “1” indicates one or more packets are
[18] rwc-_-i3
[17] rwc-_-i3
[16] rwc-_-i3
[7] rls-crw-i3 Read FIFO Underflow Status Latch = “1” indicates the RXP CPU FIFO was
[6] rls-crw-i3 Read FIFO Ready Status Latch = “1” indicates the last request to transfer data
[5] rls-crw-i3 Reserved.
[7] rwc-_-i3
[6] rwc-_-i3
[5] rwc-_-i3
Type
Description
Reserved.
Read Status Register 2. Default: 0x00.00.00.00
Reserved.
Read Queue Level = # packets currently stored in SDRAM RXP CPU Queue.
Reserved.
Read Queue Read Pointer indicates which SDRAM RXP CPU Queue packet is
to be transferred next to the internal RXP CPU FIFO (0 to 512).
Read FIFO Level = # double words currently in the RXP CPU FIFO.
Read Status Register Latch 1. Default: 0x00.00.00.00
Reserved.
data transfers from the RXP CPU Queue to the RXP CPU FIFO were
preempted/corrupted by an invalid EMA.RCR.RPCRC transfer (wait until RFRS =
1 before beginning a new RPCRC = 6 transfer operation). The combination of
RPNRSL = 1 and RPNRIE = 1 forces G.GSR1.EMARS = 1.
overflow. One or more packets were discarded from the tail of the queue. The
combination of RQOSL = 1 and RQOIE = 1 forces G.GSR1.EMARS = 1.
in the RXP CPU Queue waiting to be transferred to the RXP CPU FIFO. The
combination of RQNESL = 1 and RQNEIE = 1 forces G.GSR1.EMARS = 1.
Reserved.
read (EMRD) when no data was present in the FIFO (read when empty). The
combination of RFUSL = 1 and RFUIE = 1 forces G.GSR1.EMARS = 1.
from the SDRAM RXP CPU Queue to the RXP CPU FIFO (RPCRC = 6) is done.
The data is can be read at EMRD. The combination of RFRSL = 1 and RFRIE =
1 forces G.GSR1.EMARS = 1.
Reserved.
Read Status Register Interrupt Enable 1. Default: 0x00.00.00.00
Reserved.
Read Preempt by New Request Interrupt Enable. (see EMA.RSRL1.RPNRSL)
Read Queue Overflow Interrupt Enable. (see EMA.RSRL1.RQOSL)
Read Queue Not Empty Interrupt Enable. (see EMA.RSRL1.RQNESL)
Reserved.
Read FIFO Underflow Interrupt Enable. (see EMA.RSRL1.RFUSL)
Read FIFO Ready Interrupt Enable. (see EMA.RSRL1.RFRSL)
Reserved.
Reserved.
DS34S132 DATA SHEET
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