DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 63

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

TXP SAT/CES/Clock Only Packets can optionally include an RTP Timestamp using the RTP Exists field in the TXP
Header Descriptor Header Control (RTP is not commonly used with HDLC Bundles).
A TXP HDLC packet is generated for each HDLC packet that is received from the TDM Port with a correct HDLC
FCS value. The HDLC packet encoding is removed before the TXP Header is appended. HDLC packets that are
received with bad HDLC FCS values are discarded. HDLC TXP Packet transmission can be enable/disabled using
B.BCDR3.TXPMS.
The IP Length, IP FCS, UDP Length and UDP FCS fields are auto generated for SAT, CES, HDLC and Clock Only
packets when these fields are enabled by the TXP Header Descriptor Header Control.
9.3.3.1.1
The L-bit in the Control Word of a PW packet can be used to indicate, across the PSN, when the data contained in
a TDMoP PW payload may be corrupted (e.g. for a T1/E1 LOS condition, L-bit = 1). The
selects whether the L-bit in each TXP Packet is controlled on a “per-Bundle basis” using the TXP Header
Descriptor or on a “per-TDM Port basis” using Pn.PRCR1.LB. When the “per-Bundle” method is selected, the CPU
must modify all of the programmed TXP Header Descriptors that are associated with a TDM Port that requires an L-
bit change. When the “per-TDM Port” method is selected, changing
TXP Packets for that TDM Port.
The standards allow TXP SAT/CES PW packets, to optionally truncate/remove the payload section when the TXP
L-bit = 1 to save network bandwidth during receive TDM fault conditions (detected by the external TDM Port
Framer/LIU).
transmit rate does not change but with a smaller packet size (like that of a Clock Only packet).
9.3.3.2
The generation of TXP Bundle packets is described in the “TXP CPU Packet Interface” section.
9.3.3.3
The transmit PDV for Bundles that are used for clock recovery can be minimized to improve the clock recovery
performance at the far end by programming the TXP Bundle with the high scheduling priority (B.BCDR3.TXBPS)
and, for networks that support VLAN CoS, by assigning a high P-bit priority in the VLAN tag (the P-bit value is
provided by the CPU in the TXP Header Descriptor; high priority packets are processed before low priority
packets). Bundles that can be used for Clock Recovery include SAT/CES Bundles with payload and Clock Only
Bundles without payload. The TXP Clock Only Bundle is designed to provide the best possible transmit PDV and
latency by suppressing the payload. HDLC Bundles should normally be assigned low priority (B.BCDR3.TXBPS).
9.3.3.4
The TXP Packet Queue fill levels can be monitored using the
G.TPISR2
also provides a maskable interrupt using
9.4 CPU Packet Interface
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RXP CPU Packets that are received from the Ethernet Port are stored in an SDRAM RXP CPU Queue for the CPU
to Read. The CPU Writes TXP CPU Packets into an SDRAM TXP CPU Queue that are later transmitted at the
Ethernet Port. The depth of the RXP CPU FIFO and TXP CPU Queues are programmed at
EMI.BMCR3.PRSO.
9.4.1 RXP CPU Packet Interface
RXP CPU Packets that are received at the Ethernet Port are stored in 2 Kbyte slots in the SDRAM RXP CPU
Queue. The S132 stores an RXP CPU Header Descriptor with each RXP CPU packet to provide information about
19-4750; Rev 1; 07/11
Up to 512 stored RXP CPU packets
RXP CPU packet size up to 2000 bytes
RXP Local Timestamp
RXP Packet Classification Results
TXP CPU Packet Generation
TXP Packet Scheduling
TXP Packet Queue Monitoring
(TXP Bundle Low Priority Queue) and
L-bit Signaling
B.BCDR3.TXPMS
can be programmed to “transmit without payload”, so that the TXP Bundle packet
G.TPISRL.HPQOSL, G.TPISRL.LPQOSL
G.TPISR3
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•
(TXP CPU Queue) registers. Each of these queues
Up to 512 stored TXP CPU packets
TXP CPU packet size up to 2000 bytes
TXP RTP (OAM) Timestamp generation
G.TPISR1
Pn.PRCR1.LB
(TXP Bundle High Priority Queue),
and EMA.WSRL1.WFOSL.
changes the L-bit value in all
DS34S132 DATA SHEET
Pn.PRCR1.LBSS
EMI.BMCR3.PRSO
63 of 194
register
and