DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 71

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

Figure 9-30. MPC8313, Non-multiplexed Bus Interface
9.6.5 Interrupt Hierarchy
The S132 includes a 3-level hierarchical interrupt system for interrupting the CPU. There are more than 700
conditions that can generate an interrupt on PINT_N. The 3-level hierarchy enables the CPU to discover any active
interrupt condition with no more than 3 register reads.
The Level 3 Latched Status registers are the lowest level registers in the hierarchy and indicate when an interrupt
condition has been detected. The latched bits insure that the CPU does not “miss” transient interrupt conditions.
Real-time Status Register indications are also provided for some of the Level 3 Interrupt Conditions.
The Level 2 Status registers (G.GSR4,
interrupt conditions into Level 2 group status indications. The Level 3 registers that are combined are B.GxSRL,
JB.GxSRL,
register) bits are enabled and are indicating an active interrupt event has been detected.
The Level 1 Interrupt register, G.GSR1, combines the remaining Level 3 Latched register indications with the Level
2 group status indications so that that the CPU can read one register (G.GSR1) to monitor all latched, active Level
3 interrupt conditions. These Level 1 and Level 2 register bits are real-time (non-latched) bits to indicate when any
enabled Level 3 latched interrupt condition is active.
The Level 1 interrupt register, G.TPISRL, provides latched indications for each of its interrupt conditions. There are
no Level 3 or Level 2 registers associated with these interrupt conditions.
One Interrupt Enable bit is provided for each of the latched interrupt register bits and for each of the Level 1, real-
time
from generating an interrupt toward the CPU. When any latched register bit indicates that an active interrupt was
detected (1), that latched bit is enabled, and its associated Level 1 register bit is enabled, the S132 will generate an
active Interrupt signal (0) toward the CPU on PINT_N. The inactive state for
19-4750; Rev 1; 07/11
MPC8313
G.GSR1
LAD[10]
LAD[11]
LAD[12]
LAD[13]
LAD[14]
LAD[15]
LBCTL
LAD[0]
LAD[1]
LAD[2]
LAD[3]
LAD[4]
LAD[5]
LAD[6]
LAD[7]
LAD[8]
LAD[9]
LA[12]
LA[13]
LA[14]
LA[15]
LA[16]
LA[17]
LA[18]
LA[19]
LA[20]
LA[21]
LA[22]
LA[23]
LA[24]
LGTA
LCLK
LCSn
IRQn
G.PTSRL
register indications so that any number or combination of the interrupt conditions can be disabled
VDD33
VSS
and G.PRSRL. Each Level 2 bit indicates if any of its “group member” (Level 3 Latched
Not
used
PALE
PWIDTH
PTA_CTRL
PWRCTRL
SYSCLK
PCS_N
PRW
PTA_N
PINT_N
PD[31:16]
PD[15]
PD[14]
PD[13]
PD[12]
PD[11]
PD[10]
PD[9]
PD[8]
PD[7]
PD[6]
PD[5]
PD[4]
PD[3]
PD[2]
PD[1]
PD[0]
DS34S132
PA[13]
PA[12]
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PA[6]
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
G.GSR5
and G.GSR6) are used to combine 640 latched active Level 3
Figure 9-31. MPC8313, Multiplexed Bus Interface
MPC8313
LAD[10]
LAD[11]
LAD[12]
LAD[13]
LAD[14]
LAD[15]
LBCTL
LAD[0]
LAD[1]
LAD[2]
LAD[3]
LAD[4]
LAD[5]
LAD[6]
LAD[7]
LAD[8]
LAD[9]
LA[16]
LA[17]
LA[18]
LA[19]
LA[20]
LA[21]
LA[22]
LA[23]
LA[24]
LGTA
LCLK
LCSn
IRQn
LALE
PINT_N
VSS
signal can be programmed to
DS34S132 DATA SHEET
Not
used
PALE
PWIDTH
PTA_CTRL
PWRCTRL
SYSCLK
PCS_N
PRW
PTA_N
PINT_N
PD[31:16]
PD[15]
PD[14]
PD[13]
PD[12]
PD[11]
PD[10]
PD[9]
PD[8]
PD[7]
PD[6]
PD[5]
PD[4]
PD[3]
PD[2]
PD[1]
PD[0]
DS34S132
PA[13]
PA[12]
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PA[6]
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
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