DS34S132 Maxim Integrated Products, DS34S132 Datasheet
DS34S132
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DS34S132 Summary of contents
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... Rev 0; 7/09 www.DataSheet4U.com General Description The IETF PWE3 SAToP/CESoPSN/HDLC-compliant DS34S132 provides the interworking functions that are required for translating TDM data streams into and out of TDM-over-Packet (TDMoP) data streams for L2TPv3/IP, UDP/IP, MPLS (MFA-8), and Metro Ethernet (MEF-8) networks while meeting the jitter and wander timing performance that is required by the public network (ITU G ...
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... TDM timing and the nature of the data can be described as “packetized” as with Ethernet, Frame Relay and ATM services. For clarity the HDLC service is categorized as “HDLC over PW”. One example Legacy HDLC service is SS7 Signaling which is used to communicate voice signaling information from one TDM switch to another. 19-4750; Rev 0; 7/09 DS34S132 DATA SHEET 8 of 194 ...
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... MFA – MPLS/Frame Relay Alliance (Now called IP/MPLS Forum) MII – Medium Independent Interface (IEEE 802.3) 19-4750; Rev 0; 7/09 DS34S132 DATA SHEET MPLS – Multi-Protocol Label Switching OAM – Operations, Administration & Maintenance OCXO – Oven Controlled Crystal Oscillator ...
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... Emulation of TDM Circuits over MPLS Using Raw Encapsulation – Implement. Agree. (11/2004) MFA 8.0.0 Note: Only those sections of these standards that are affected by the DS34S132 functions are considered applicable. For example, several of the standards specify T1/E1 Framer/LIU functions (e.g. pulse shape) that are not included in the DS34S132 but also specify jitter/wander functions that are applicable. ...
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... HDLC encoding and forward the data over an HDLC PW. The DS34S132 incorporates 256 HDLC Engines so that any PW can be assigned as a TDMoP HDLC PW. PW Termination points often must also terminate OAM and Signaling packet data streams. To support this need ...
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... Maxim Integrated Products Confidential and Proprietary www.DataSheet4U.com The DS34S132 uses an external DDR SDRAM device to buffer data. The large memory supplies sufficient buffer space to support a 256 ms PDV for each of the 256 PW/Bundles and to enable packet re-ordering for packets that are received out of order (the PSN may mis-order the packets). This large memory is also used to buffer the HDLC data streams and the CPU terminated OAM and Signaling packets ...
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... The Maxim TDMoP family of devices offers a range of density solutions so that lower density solutions like the DS34T101 can be used in Service Provider Edge applications, to support a small number of T1/E1 lines, and higher density solutions like the DS34S132 can be used in Central Office applications, to terminate several Service Provider Edge nodes. PWs can be carried over fiber, wireless, SONET/SDH, G/EPON, coax, etc. ...
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... Communications platforms with all/any of the above-mentioned capabilities can replace obsolete, low bandwidth TDM buses with low cost, high bandwidth Ethernet buses. The DS34S132 provides the interworking functions that are needed to packetize TDM services so that they can be multiplexed together with bursty services for transmission over a unified backplane bus ...
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... Maxim Integrated Products Confidential and Proprietary www.DataSheet4U.com 6 BLOCK DIAGRAM Figure 6-1. DS34S132 Functional Block Diagram LIUCLK TCLKO[31:0] EXTCLK[1:0] TDM TSYNC[31:0] Port TDM & TDAT[31:0] Port TSA & TSIG[31:0] 1 TSA 32 RCLK[31:0] TDM Port RSYNC[31:0] TDM & RDAT[31:0] Port TSA & RSIG[31:0] 1 TSA 32 JTAG 19-4750 ...
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... Per Timeslot CPU Controlled CAS (CPU inserts CAS; in TXP and/or RXP directions) CAS Status and Change of Status for CPU Monitoring (in RXP and TXP directions) Data Conditioning – can force any 8-bit pattern on any number of Timeslots (in RXP and TXP directions) 19-4750; Rev 0; 7/09 DS34S132 DATA SHEET 16 of 194 ...
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... Unstructured PW Payload (without framing; SAToP): E1, T1 and slower TDM bit rate (≤ 2.048 Mb/s) Structured PW Payload (with framing; CESoPSN) E1, T1-SF and T1-ESF formats 19-4750; Rev 0; 7/09 UDP / IPv4 MEF (MEF-8) UDP / IPv6 MPLS (MFA-8) DS34S132 DATA SHEET 17 of 194 ...
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... MPC8xx or MPC83xx synchronous interface using MHz clock rate (the MPC8xx and MPC83xx are processor product families of Freescale Semiconductor, Inc.) Selectable 16-bit or 32-bit data bus DS34S132 device Control & Sense Registers Mask-able Interrupt Hierarchy for Change of Status, Alarms and Events Ethernet Port RMON Statistics Miscellaneous ...
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... DDR SDRAM Interface that does not require any glue-logic IEEE 1149.1 JTAG support MBIST (memory built-in self test) 1.8V Core, 2.5V DDR SDRAM and 3.3V I/O that are 5V tolerant mm, 676-pin BGA package (1mm pitch) 19-4750; Rev 0; 7/09 DS34S132 DATA SHEET 19 of 194 ...
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... Maxim Integrated Products Confidential and Proprietary www.DataSheet4U.com 8 PIN DESCRIPTIONS 8.1 Short Pin Descriptions Table 8-1. DS34S132 Short Pin Descriptions * Name Type TDM Port through 31 Ports TCLKOn Oz TSYNCn IO TDATn Oz TSIGn Oz RCLKn I RSYNCn IO RDATn I RSIGn I 100/1000 Mbps Ethernet MAC Interface (GMII/MII) TXCLK Ipu GTXCLK ...
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... CLAD 1.8 Volt Power (may be connected to AVDD) CVDD Ground (may be connected to AVSS) SDRAM Digital Core 2.5 Volt Power Supply Input SDRAM DQ 2.5 Volt Power Supply Input SDRAM Digital Ground for VDDP and VDDQ SDRAM SSTL_2 Reference Voltage (one-half VDDQ) DS34S132 DATA SHEET 21 of 194 ...
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... The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE 676 TEPBGA (27mm x 27mm) Figure 15-1. 676-Ball TEPBGA 19-4750; Rev 0; 7/09 PACKAGE CODE — DS34S132 DATA SHEET DOCUMENT NO. 21-0311 192 of 194 ...
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... Theta-JA, Still Air Theta-JC, Still Air Psi Jt (Junction to Top of Case) Note 1: Theta-JA is based on the package mounted on a four-layer JEDEC board and measured in a JEDEC test chamber. 19-4750; Rev 0; 7/09 DS34S132 DATA SHEET Value -40C to +85C -40C to +125C 14.5C/W (Note 1) 3.9C/W 0.23 ...
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... 2009 Maxim Integrated Products DS34S132 DATA SHEET DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products ...