DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 147

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

10.3.15.7 Port n Receive Status Register Latches (Pn.)
Table 10-36. Port n Receive Status Register Latches (Pn.)
10.3.15.8 Port n Receive Status Register Interrupt Enables (Pn.)
Table 10-37. Port n Receive Status Register Interrupt Enables (Pn.)
10.3.16 Timeslot Assignment Registers (TSAn.m.; “n” = TDM Port n; “m” = Timeslot m)
Table 10-38. Timeslot Assignment Registers (TSAn.m.; “n” = TDM Port n; “m” = Timeslot m)
Note:
19-4750; Rev 1; 07/11
Pn. Field
Name
CTS30
CTS31
Pn. Field
Name
PRSRL.
RSVD
BOSL
COFASL
Pn. Field
Name
PRSRIE.
RSVD
BOIE
COFAIE
TSAn.m.
Field Name
CR.
RSVD
TSAS
RSVD
BNS
1
There are 1024 TSAn.m. registers (32 TDM Ports * 32 Timeslots = 1024). The TSAn.m. address = 3000h+ (n*0020h +
m*0004h) where the TDM Port “n” varies from 0 to 0x1F and the TS “m” varies from 0 to 0x1F. In binary this can
viewed as 11.00P
bit TS # (0 – 31 decimal; T1 does not use the values 24 – 31). For an Unstructured TDM Port (SAT or HDLC) TS 0
must be assigned.
Addr (A:)
Bit [x:y]
Addr (A:)
Bit [x:y]
A:2070h
Addr (A:)
Bit [x:y]
A:2078h
Addr (A:)
Bit [x:y]
A
+n*0020h
+m*0004h
1
[31:2]
[31:2]
:3000h
[7:4] ros-_-_
[3:0] ros-_-_
[31:17]
[1] rls-crw-i3
[0] rls-crw-i3
[1] rwc-_-i3
[0] rwc-_-i3
[15:8]
[7:0] rwd-_-_ Bundle Number Select = Bundle # for TDM Port “n”, Timeslot “m” (for TSAS = 1).
[16] rwd-_-_ Timeslot Assigned Select = “1” = TDM Port “n” Timeslot “m” is assigned to the
Type
Type
Type
4
P
Type
3
.P
2
P
1
P
0
T
Description
Configuration Register. Default: na (SRAM unknown values after reset)
Reserved.
Bundle # specified by BNS (“0” = unassigned/unused).
Reserved.
4
Description
CAS Time Slot 30 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 30
CAS Time Slot 31 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 31
Description
Port Receive Status Register Latch. Default: 0x00.00.00.00
Reserved.
Buffer Overrun Status Latch = “1” indicates the receive TDM Port received data
faster than it could be processed (TXP payload data was lost).
Change Of Frame Alignment Status Latch = “1” indicates a change of frame or
multi-frame timing error was detected (only valid for SFS = 1).
Description
Port Receive Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Buffer Overrun Interrupt Enable. The combination of BOIE = 1 and
PRSRL.BOSL = 1 forces G.GSR1.PS = 1.
Change Of Frame Alignment Interrupt Enable. The combination of and
COFAIE = 1 and PRSRL.COFASL = 1 forces G.GSR1.PS = 1.
.T
3
T
2
T
1
T
0
where P
4
P
3
P
2
P
1
P
0
= 5-bit TDM Port # (0 – 31 decimal) and T
DS34S132 DATA SHEET
4
T
3
T
147 of 194
2
T
1
T
0
= 5-