DS34S132GNA2+ Maxim Integrated, DS34S132GNA2+ Datasheet - Page 133

• Manufacturer Part Number: DS34S132GNA2+
• Description: Communication ICs - Various 32Port TDM-Over-Pack Transport Device
• Manufacturer: Maxim Integrated

Specifications of DS34S132GNA2+

• Rohs: yes
• Part # Aliases: 90-34S13+2N2

19-4750; Rev 1; 07/11
M. Field Name
MSK_IRQ_RX_USED
MSK_IRQ_RX_DONE
MSK_IRQ_MAN_D
ONE
PHY_MAN.
PHY_SET3
PHY_CL22
PHY_SET2
PHY_ADDR
PHY_REG_ADDR
PHY_SET1
PHY_DATA_WR
RX_PAUSE_TIME. A:0C38h
RSVD
RX_PAUSE_Q
TX_PAUSE_QUAN
T.
RSVD
TX_PAUSE_Q
HASH_BOT.
HASH_BOT
HASH_TOP.
HASH_TOP
LADDR1_BOT.
SPEC_ADD1_BOT
LADDR1_TOP.
RSVD
SPEC_ADD1_TOP
LADDR2_BOT.
SPEC_ADD2_BOT
LADDR2_TOP.
RSVD
SPEC_ADD2_TOP
LADDR3_BOT.
SPEC_ADD3_BOT
LADDR3_TOP.
RSVD
SPEC_ADD3_TOP
LADDR4_BOT.
SPEC_ADD4_BOT
Addr (A:)
Bit [x:y]
A:0C34h
A:0C3Ch
A:0C80h
A:0C84h
A:0C88h
A:0C8Ch
A:0C90h
A:0C94h
A:0C98h
A:0C9Ch
A:0CA0h
[29:28] rwc-_-_
[27:23] rwc-_-_
[22:18] rwc-_-_
[17:16] rwc-_-_
[31:16]
[31:16]
[31:16]
[31:16]
[31:16]
[15:0] rwc-_-_
[15:0] ros-_-_
[15:0] rwc-_-_
[31:0] rwc-_-_
[31:0] rwc-_-_
[31:0] rwc-_-_
[15:0] rwc-_-_
[31:0] rwc-_-_
[15:0] rwc-_-_
[31:0] rwc-_-_
[15:0] rwc-_-_
[31:0] rwc-_-_
[31] rwc-_-_
[30] rwc-_-_
[2] ros-_-_
[1] ros-_-_
[0] ros-_-_
Type
Description
Reserved.
Reserved.
Mask PHY Management Operation Complete. A read of this register
returns the value of the management done interrupt mask. 0: Interrupt is
enabled 1: Interrupt is disabled A write to this register directly affects the
state of the corresponding bit in the interrupt status register, causing an
interrupt to be generated if a 1 is written.
Phy Maintenance Register. Default: 0x00.00.00.00
Reserved.
Reserved. This must be programmed to “1”.
Phy Set 2 selects the MDIO Operation: 2 = Read; 1 = Write.
Phy Address selects the MDIO Phy address.
Phy Register Address selects the MDIO Register address.
Reserved. This must be programmed to “2”.
Phy Data to be Written provides the Write data sent to the Phy or the
Read data received from the Phy according to the PHY_SET2 operation.
Received Pause Quantum Register. Default: 0x00.00.00.00
Reserved.
Reserved.
Transmit Pause Quantum Register. Default: 00.00.FF.FFh
Reserved.
Reserved.
Hash Register Bottom. Default: 0x00.00.00.00
Reserved.
Hash Register Top. Default: 0x00.00.00.00
Reserved.
Specific Address 1 Bottom. Default: 0x00.00.00.00
Reserved.
Specific Address 1 Top. Default: 0x00.00.00.00
Reserved.
Reserved.
Specific Address 2 Bottom. Default: 0x00.00.00.00
Reserved.
Specific Address 2 Top. Default: 0x00.00.00.00
Reserved.
Reserved.
Specific Address 3 Bottom. Default: 0x00.00.00.00
Reserved.
Specific Address 3 Top. Default: 0x00.00.00.00
Reserved.
Reserved.
Specific Address 4 Bottom. Default: 0x00.00.00.00
Reserved.
DS34S132 DATA SHEET
133 of 194