ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 89

• Manufacturer Part Number: ST92F120V1Q7
• Description: Microcontrollers (MCU) Flash 128K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST92F120V1Q7

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 16 Channel
• Lead Free Status / Rohs Status: No

6 ON-CHIP DIRECT MEMORY ACCESS (DMA)
6.1 INTRODUCTION
The ST9 includes on-chip Direct Memory Access
(DMA) in order to provide high-speed data transfer
between peripherals and memory or Register File.
Multi-channel DMA is fully supported by peripher-
als having their own controller and DMA chan-
nel(s). Each DMA channel transfers data to or
from contiguous locations in the Register File, or in
Memory. The maximum number of bytes that can
be transferred per transaction by each DMA chan-
nel is 222 with the Register File, or 65536 with
Memory.
The DMA controller in the Peripheral uses an indi-
rect addressing mechanism to DMA Pointers and
Counter Registers stored in the Register File. This
is the reason why the maximum number of trans-
actions for the Register File is 222, since two Reg-
isters are allocated for the Pointer and Counter.
Register pairs are used for memory pointers and
counters in order to offer the full 65536 byte and
count capability.
Figure 40. DMA Data Transfer
GROUP F
PERIPHERAL
PAGED
REGISTERS
REGISTER FILE
PERIPHERAL
DATA
ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
DF
0
REGISTER FILE
COUNTER
ADDRESS
6.2 DMA PRIORITY LEVELS
The 8 priority levels used for interrupts are also
used to prioritize the DMA requests, which are ar-
bitrated in the same arbitration phase as interrupt
requests. If the event occurrence requires a DMA
transaction, this will take place at the end of the
current instruction execution. When an interrupt
and a DMA request occur simultaneously, on the
same priority level, the DMA request is serviced
before the interrupt.
An interrupt priority request must be strictly higher
than the CPL value in order to be acknowledged,
whereas, for a DMA transaction request, it must be
equal to or higher than the CPL value in order to
be executed. Thus only DMA transaction requests
can be acknowledged when the CPL=0.
DMA requests do not modify the CPL value, since
the DMA transaction is not interruptable.
REGISTER FILE
TRANSFERRED
MEMORY
DATA
OR
COUNTER VALUE
START ADDRESS
VR001834
89/324
9