ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 206

• Manufacturer Part Number: ST92F120V1Q7
• Description: Microcontrollers (MCU) Flash 128K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST92F120V1Q7

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 16 Channel
• Lead Free Status / Rohs Status: No

SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.4 Functional Description
Figure 2
(SPI) block diagram.
This interface contains 4 dedicated registers:
Refer to the SPCR, SPPR, SPSR and SPDR reg-
isters in
10.6.4.1 Master Configuration
In a master configuration, the serial clock is gener-
ated on the SCK pin.
Procedure
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– A Control Register (SPCR)
– A Prescaler Register (SPPR)
– A Status Register (SPSR)
– A Data Register (SPDR)
– Define the serial clock baud rate by setting/re-
– Select the CPOL and CPHA bits to define one
– The SS pin must be connected to a high level
– The MSTR and SPOE bits must be set (they
setting the DIV2 bit of SPPR register, by writ-
ing a prescaler value in the SPPR register and
programming the SPR0 & SPR1 bits in the
SPCR register.
of the four relationships between the data
transfer and the serial clock (see
signal during the complete byte transmit se-
quence.
remain set only if the SS pin is connected to a
high level signal).
Section 0.1.6
shows the serial peripheral interface
for the bit definitions.
Figure
4).
In this configuration the MOSI pin is a data output
and the MISO pin is a data input.
Transmit Sequence
The transmit sequence begins when a byte is writ-
ten the SPDR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPDR register is
read, the SPI peripheral returns this buffered val-
ue.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPSR register while the SPIF
2. A read of the SPDR register.
Note: While the SPIF bit is set, all writes to the
SPDR register are inhibited until the SPSR regis-
ter is read.
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIS and SPIE
bit is set
bits are set.