ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet
ST92F120V1Q7
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ST92F120V1Q7 Summary of contents
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Memories – Internal Memory 128 Kbytes Single Voltage FLASH Kbytes RAM, 1K byte emulated EEPROM (E3PROM – 224 general purpose registers (register file) available as RAM, accumulators or index pointers Clock, Reset and Supply Management ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... ST92F120 - GENERAL DESCRIPTION 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST92F120 microcontroller is developed and manufactured by STMicroelectronics using a pro- prietary n-well HCMOS process. Its performance derives from the use of a flexible 256-register pro- gramming model for ultra-fast context switching and real-time event response. The intelligent on- ...
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Figure 1. ST92F120JV: Architectural Block Diagram FLASH 60/128 Kbytes EEPROM 1K byte RAM 2/4 Kbytes 256 bytes WAIT Register File NMI RW 8/16 bit DS2 CPU Interrupt INT[6:0] Management WKUP[15:0] ST9 CORE OSCIN OSCOUT RESET RCCU CLOCK2/8 ...
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ST92F120 - GENERAL DESCRIPTION 1.2 PIN DESCRIPTION AS. Address Strobe (output, active low, 3-state). Address Strobe is pulsed low once at the begin- ning of each memory cycle. The rising edge of AS indicates that address, Read/Write (RW), and Data ...
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Figure 2. CMOS Basic Inverter OUT When an input is kept at logic zero, the N-channel transistor is off, while the P-channel is on and can conduct. The opposite occurs when an input is ...
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... STMicroelectronics internal Quality Assurance standards and recommendations. 1.2.4.2 Protective Interface Although ST9 input/output circuitry has been de- signed taking ESD and Latchup problems into ac- Figure 3 ...
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Internal Circuitry: Digital I/O pin In Figure 3 a schematic representation of an ST9 pin able to operate either as an input out- put is shown. The circuitry implements a standard input buffer and a push-pull ...
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ST92F120 - GENERAL DESCRIPTION In Figure 5 a true open-drain pin schematic is shown. In this case all paths to V (P-channel driver, ESD protection diode, internal weak pull-up) in order to allow the system to turn off the power ...
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Power Supply and Ground As already said for the I/O pins, in order to guaran- tee ST9 compliancy with respect to Quality Assur- ance recommendations concerning ESD and Latchup, dedicated circuits are added to the differ- ent power supply ...
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ST92F120 - GENERAL DESCRIPTION Figure 7. ST92F120: Pin Configuration (Top-view PQFP100) 100 99 RXCLK1/P9.3 1 DCD1/P9.4 2 RTS1/P9.5 3 CLOCK2/P9.6 4 P9.7 5 WAIT/WKUP5/P5.0 6 WKUP6/WDOUT/P5.1 7 SIN0/WKUP2/P5.2 8 WDIN/SOUT0/P5.3 9 TXCLK0/CLKOUT0/P5.4 10 RXCLK0/WKUP7/P5.5 11 DCD0/WKUP8/P5.6 12 WKUP9/RTS0/P5.7 13 ICAPA1/P4.0 ...
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Table 1. ST92F120 Power Supply Pins Name Function Main Power Supply Voltage pins internally connected) Digital Circuit Ground V SS (pins internally connected) AV Analog Circuit Supply Voltage DD AV Analog Circuit Ground SS Must be kept ...
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ST92F120 - GENERAL DESCRIPTION 1.3 I/O PORTS Port 0 and Port 1 provide the external memory in- terface. All the ports of the device can be pro- grammed as Input/Output or in Input mode, com- patible with TTL or CMOS ...
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How to Configure the I/O Ports To configure the I/O ports, use the information in Table 3, Table 4 and the Port Bit Configuration Ta- ble in the I/O Ports Chapter (See Input Note = the hardware characteristics fixed for ...
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ST92F120 - GENERAL DESCRIPTION Table 4. I/O Port Alternate Functions Port General Name Purpose I/O P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 All ports useable for general pur- P2.1 pose ...
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Port General Pin No. Name Purpose I/O P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 All ports useable for general pur- pose I/O (input, P5.3 output or bidirec- tional) P5.4 P5.5 P5.6 P5.7 P6.0 P6.1 P6.2 ST92F120 - ...
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ST92F120 - GENERAL DESCRIPTION Port General Name Purpose I/O P6.3 P6.4 P6.5 P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 All ports useable for general pur- pose I/O (input, P8.0 output or bidirec- tional) P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 ...
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OPERATING MODES To optimize the performance versus the power consumption of the device, the ST92F120 sup- ports different operating modes that can be dy- namically selected depending on the performance and functionality requirements of the application at a given ...
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ST92F120 - DEVICE ARCHITECTURE 2 DEVICE ARCHITECTURE 2.1 CORE ARCHITECTURE The ST9 Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean ...
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MEMORY SPACES (Cont’d) Figure 10. Register Groups 255 F PAGED REGISTERS 240 239 E SYSTEM REGISTERS 224 223 Figure 12. Addressing the Register ...
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ST92F120 - DEVICE ARCHITECTURE MEMORY SPACES (Cont’d) 2.2.2 Register Addressing Register File registers, including Group F paged registers (but excluding Group D), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus R231, RE7h ...
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SYSTEM REGISTERS The System registers are listed in Registers (Group E). They are used to perform all the important system settings. Their purpose is de- scribed in the following pages. Refer to the chapter dealing with I/O for a ...
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ST92F120 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) 2.3.2 Flag Register The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the ...
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SYSTEM REGISTERS (Cont’d) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a Sdm instruction. Note that ...
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ST92F120 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) 7 RG4 RG3 RG2 RG1 RG0 Bits 7:3 = RG[4:0]: Register Group number. These bits contain the ...
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SYSTEM REGISTERS (Cont’d) Figure 13. Pointing to a single group of 16 registers REGISTER BLOCK GROUP NUMBER REGISTER FILE r15 3 ...
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ST92F120 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) 2.3.4 Paged Registers pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always ...
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Note: Setting the HIMP bit is recommended for noise reduction when only internal Memory is used. If the memory access ports are declared as an ad- dress AND as an I/O port (for example: P10... P14 = Address, and P15... ...
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ST92F120 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) USER STACK POINTER HIGH REGISTER (USPHR) R236 - Read/Write Register Group: E (System) Reset value: undefined 7 USP15 USP14 USP13 USP12 USP11 USP10 USP9 USER STACK POINTER LOW REGISTER (USPLR) R237 - Read/Write ...
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MEMORY ORGANIZATION Code and data are accessed within the same line- ar address space. All of the physically separate memory areas, including the internal ROM, inter- nal RAM and external memory are mapped in a common address space. The ...
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ST92F120 - DEVICE ARCHITECTURE 2.5 MEMORY MANAGEMENT UNIT The CPU Core includes a Memory Management Unit (MMU) which must be programmed to per- form memory accesses (even if external memory is not used). The MMU is controlled by 7 registers ...
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ADDRESS SPACE EXTENSION To manage 4 Mbytes of addressing space necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address into a 22-bit physical ...
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ST92F120 - DEVICE ARCHITECTURE ADDRESS SPACE EXTENSION (Cont’d) 2.6.2 Addressing 64-Kbyte Segments This extension mode is used to address Data memory space during a DMA and Program mem- ory space during any code execution (normal code and interrupt routines). Three ...
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MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set. 7 DPR0 DPR0 DPR0 DPR0 DPR0 Bits 7:0 ...
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ST92F120 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) 2.7.2 CSR: Code Segment Register This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruc- tion has ...
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MMU REGISTERS (Cont’d) Figure 20. Memory Addressing Scheme (example) DPR3 DPR2 DPR1 DPR0 DMASR ISR CSR ST92F120 - DEVICE ARCHITECTURE 4M bytes 16K 16K 16K 64K 64K 16K 64K 3FFFFFh 294000h 240000h 23FFFFh 20C000h 200000h 1FFFFFh 040000h 03FFFFh 030000h 020000h ...
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ST92F120 - DEVICE ARCHITECTURE 2.8 MMU USAGE 2.8.1 Normal Program Execution Program memory is organized as a set of 64- Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, ...
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SINGLE VOLTAGE FLASH & EEPROM 3.1 INTRODUCTION The Flash circuitry contains one array divided in two main parts that can each be read independ- ently. The first part contains the main Flash array for code storage, a reserved array ...
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM 3.2 FUNCTIONAL DESCRIPTION 3.2.1 Structure The Flash memory is composed of three parts (see following table): – 1 reserved sector for system routines (TestFlash including user OTP area) – 4 main sectors for ...
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FUNCTIONAL DESCRIPTION (Cont’d) 3.2.3 Operation The memory has a register interface mapped in memory space (segment 22h). All operations are enabled through the FCR (Flash Control Register) ECR (EEPROM Control Register). All operations on the Flash must be executed from ...
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM 3.3 REGISTER DESCRIPTION 3.3.1 Control Registers FLASH CONTROL REGISTER (FCR) Address: 224000h - Read/Write Reset value: 0000 0000 (00h FWM FPAG FCHI FBYT FSEC ...
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REGISTER DESCRIPTION (Cont’d) When in Erase Suspend the memory accepts only the following operations: Read, Erase Resume and Byte Program. Updating the EEPROM memo not possible during a Flash Erase Suspend. The FSUSP bit must be reset (and ...
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM REGISTER DESCRIPTION (Cont’d) Bit 2 = WFIS: Wait For Interrupt Status. If this bit is reset, the WFI instruction puts the Flash macrocell in Stand-by mode (immediate read possible, but higher consumption: 100 ...
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REGISTER DESCRIPTION (Cont’d) 3.3.2 Status Registers During a Flash or an EEPROM write operation any attempt to read the memory under modification will output invalid data (FFh equivalent to a NOP in- struction). This means that the Flash memory is ...
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM REGISTER DESCRIPTION (Cont’d) Bit 5 = SWER. Swap or 1 over 0 Error (Read On- ly). This bit has two different meanings, depending on whether the current write operation is to Flash or ...
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WRITE OPERATION EXAMPLE Each operation (both Flash and EEPROM) is acti- vated by a sequence of instructions like the follow- ing: OR CR, #OPMASK ;Operation selection LD ADD1, #DATA1 ;1st Add and Data LD ADD2, #DATA2 ;2nd Add and ...
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM 3.5 EEPROM 3.5.1 Hardware EEPROM Emulation Note: This section provides general information only. Users do not have to be concerned with the hardware EEPROM emulation. The last 256 bytes of the two EEPROM ...
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EEPROM (Cont’d) 3.5.2 EEPROM Update Operation The update of the EEPROM content can be made by pages of 16 consecutive bytes. The Page Up- date operation allows bytes to be loaded into the RAM buffer that replace ...
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM 3.6 PROTECTION STRATEGY The protection bits are stored in the last 4 loca- tions of the TestFlash (from 231FFCh) (see 25). All the available protections are forced active dur- ing reset, then in ...
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PROTECTION STRATEGY (Cont’d) Bits 2:0 = PWT[2:0]: Password Attempt 2-0. If the TMDIS bit in the NVWPR register (231FFDh) is programmed to 0, every time a Set Protection operation is executed with Program Addresses equal to NVPWD1-0 (231FFE-Fh), the two ...
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM (231FFDh). The second write access, with Pro- gram Data matching with NVPWD[1:0] content, re- sets the PWOK bit of NVWPR. These two registers can be accessed only in write mode (a read access ...
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Register Value BRGLR - R253 04h Baud Rate Divider is 4 SICR - R254 83h Synchronous Mode SOCR - R255 01h In addition, the Code Update routine remaps the interrupts in the TestFlash (ISR = 23h), and config- ures I/O ...
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ST92F120 - REGISTER AND MEMORY MAP 4 REGISTER AND MEMORY MAP 4.1 INTRODUCTION The ST92F120 register map, memory map and peripheral options are documented in this section. Use this reference information to supplement the functional descriptions given elsewhere in this ...
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... Figure 27. ST92F120JV1Q7/ST92F120V1Q7 User Memory Map (part 1) SECTOR F3 8 Kbytes SECTOR F2 8 Kbytes SECTOR F1 48 Kbytes SECTOR F0 64 Kbytes SEGMENT 22h 64 Kbytes ST92F120 - REGISTER AND MEMORY MAP 01FFFFh 01C000h 01BFFFh SEGMENT 1h 018000h 017FFFh 64 Kbytes 014000h 013FFFh 010000h 00FFFFh 00C000h 00BFFFh SEGMENT 0h 008000h ...
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... ST92F120 - REGISTER AND MEMORY MAP Figure 28. ST92F120JV1Q7/ST92F120V1Q7 User Memory Map (part 2) SEGMENT 23h 64 Kbytes SEGMENT 22h 64 Kbytes 56/324 9 23FFFFh 23C000h 23BFFFh 238000h 237FFFh 234000h 233FFFh 230000h 231FFFh 230000h TESTFLASH - 8 Kbytes 231FFFh 231F80h FLASH OTP - 128 bytes 231FFFh 231FFCh FLASH OTP Protection - 4 bytes ...
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Figure 29. ST92F120 User Memory Map (part 3) SEGMENT 20h 64 Kbytes 4.3 ST92F120 REGISTER MAP Table 15 contains the map of the group F periph- eral pages. The common registers used by each peripheral are listed in Table 14. ...
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ST92F120 - REGISTER AND MEMORY MAP Table 15. Group F Pages Register Map Resources available on the ST92F120 device: Reg R255 Res R254 Res. R253 R252 R251 Res R250 Res. R249 R248 R247 Res. Res. ...
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Table 16. Detailed Register Map Page Reg. Block No. (Dec) R230 R231 R232 R233 R234 Core R235 R236 R237 N/A R238 R239 R224 R225 I/O R226 Port R227 0:5 R228 R229 R242 R243 R244 INT R245 R246 0 R247 R248 ...
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ST92F120 - REGISTER AND MEMORY MAP Page Reg. Block No. (Dec) R240 I/O Port R241 4 R242 R244 I/O Port R245 5 R246 R248 3 I/O R249 Port R250 6 R251 R252 I/O R253 Port R254 7 R255 R240 R241 ...
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Page Reg. Register Block No. Name (Dec) R240 REG0HR1 R241 REG0LR1 R242 REG1HR1 R243 REG1LR1 R244 CMP0HR1 R245 CMP0LR1 R246 CMP1HR1 R247 CMP1LR1 8 R248 TCR1 R249 TMR1 MFT1 R250 T_ICR1 R251 PRSR1 R252 OACR1 R253 OBCR1 R254 T_FLAGR1 R255 ...
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ST92F120 - REGISTER AND MEMORY MAP Page Reg. Block No. (Dec) R240 R241 11 STIM R242 R243 R240 R241 R242 R243 R244 R245 R246 R247 20 I2C R248 R249 R250 R251 R252 R253 R254 I2CECCR R255 R240 R241 R242 MMU ...
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Page Reg. Register Block No. Name (Dec) R240 STATUS R241 TXDATA R242 RXDATA R243 TXOP R244 CLKSEL R245 CONTROL R246 PADDR R247 ERROR 23 JBLPD R248 IVR R249 PRLR R250 IMR R251 OPTIONS R252 CREG0 R253 CREG1 R254 CREG2 R255 ...
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ST92F120 - REGISTER AND MEMORY MAP Page Reg. Block No. (Dec) R240 R241 R242 R243 R244 R245 R246 R247 25 SCI1 R248 R248 R249 R250 R251 R252 R253 R254 R255 R240 R241 R242 R243 R244 R245 R246 R247 28 EFT0 ...
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Page Reg. Register Block No. Name (Dec) R240 IC1HR1 R241 IC1LR1 R242 IC2HR1 R243 IC2LR1 R244 CHR1 R245 CLR1 R246 ACHR1 R247 ACLR1 29 EFT1 R248 OC1HR1 R249 OC1LR1 R250 OC2HR1 R251 OC2LR1 R252 CR1_1 R253 CR2_1 R254 SR1 R255 ...
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ST92F120 - REGISTER AND MEMORY MAP Page Reg. Block No. (Dec) R240 R241 R242 R243 R244 R245 R246 R247 61 A/D 1 R248 R249 R250 R251 R252 R253 R254 R255 R240 R241 R242 R243 R244 R245 R246 R247 63 A/D ...
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INTERRUPTS 5.1 INTRODUCTION The ST9 responds to peripheral and external events through its interrupt channels. Current pro- gram execution can be suspended to allow the ST9 to execute a specific response routine when such an event occurs, providing that ...
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ST92F120 - INTERRUPTS 5.2.2 Segment Paging Routines The ENCSR bit in the EMR2 register can be used to select between original ST9 backward compati- bility mode and ST9+ interrupt management mode. ST9 Backward Compatibility Mode (ENCSR ENCSR is ...
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Table 17 Table 17. Daisy Chain Priority Highest Position INTA0 / Watchdog Timer INTA1 / Standard Timer INTB0 / Extended Function Timer 0 INTB1 / Extended Function Timer 1 INTC0 ...
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ST92F120 - INTERRUPTS ARBITRATION MODES (Cont’d) re-enabled, they will be acknowledged regardless of the interrupt service routine’s priority. This may cause undesirable interrupt response sequences. Examples In the following two examples, three interrupt re- quests with different priority levels (2, ...
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ARBITRATION MODES (Cont’d) Example 2 In the second example, (more complex, 33), each interrupt service routine sets Interrupt Enable with the ei instruction at the beginning of the routine. Placed here, it minimizes response time for requests with a higher ...
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ST92F120 - INTERRUPTS ARBITRATION MODES (Cont’d) 5.5.2 Nested Mode The difference between Nested mode and Con- current mode, lies in the modification of the Cur- rent Priority Level (CPL) during interrupt process- ing. The arbitration phase is basically identical to ...
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ARBITRATION MODES (Cont’d) End of Interrupt Routine The iret Interrupt Return instruction executes the following steps: – The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system stack. – The PC high ...
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ST92F120 - INTERRUPTS 5.6 EXTERNAL INTERRUPTS 5.6.1 Standard External Interrupts The standard ST9 core contains 8 external inter- rupts sources grouped into four pairs. Table 18. External Interrupt Channel Grouping External Channel Interrupt WKUP[0:15] INTD1 P6[7,5] P5[7:5, 2:0] P4[7,4] INT6 ...
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EXTERNAL INTERRUPTS (Cont’d) Figure 37. External Interrupts Control Bits and Vectors Watchdog/Timer End of count TEA0 INT 0 pin* TEA1 STD Timer INT 1 pin* TEB0 EFT0 Timer INT 2 pin* TEB1 EFT1 Timer INT 3 pin* TEC0 EEPROM/Flash INT ...
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ST92F120 - INTERRUPTS 5.7 TOP LEVEL INTERRUPT The Top Level Interrupt channel can be assigned either to the external pin NMI or to the Timer/ Watchdog according to the status of the control bit EIVR.TLIS (R246.2, Page 0). If this ...
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INTERRUPT RESPONSE TIME The interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. One more CPUCLK cycle is required when an interrupt is acknowledged. Requests are sampled every 5 CPUCLK cycles. If the ...
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ST92F120 - INTERRUPTS 5.10 INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: System Reset value: 1000 0111 (87h) 7 GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0 Bit 7 = GCEN: Global Counter Enable. This bit ...
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INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT PENDING REGISTER (EIPR) R243 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) 7 IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0 Bit 7 = IPD1: INTD1 Interrupt Pending bit Bit 6 = IPD0: ...
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ST92F120 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110b (x6h TLTEV TLIS IAOS EWEN Bits 7:4 = V[7:4]: Most significant nibble of Exter- ...
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) 5.11.1 Introduction The Wake-up/Interrupt Management Unit extends the number of external interrupt lines from (depending on the number of external interrupt lines mapped on external pins of the device). ...
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ST92F120 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 5.11.3 Functional Description 5.11.3.1 Interrupt Mode To configure the 16 wake-up lines as interrupt sources, use the following procedure: 1. Configure the mask bits of the 16 wake-up lines (WUMRL, ...
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) Case 3: NMI = 1 (NMI kept high during the 3rd write instruction of the sequence), bad STOP bit setting sequence The result is the same as Case 1: STOP = 0, EX_STP ...
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ST92F120 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 5.11.3.4 NMI Pin Management On the CPU side, if TLTEV=1 (Top Level Trigger Event, bit 3 of register R246, page 0) then a rising edge on the NMI pin will ...
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 5.11.4 Programming Considerations The following paragraphs give some guidelines for designing an application program. 5.11.4.1 Procedure for Entering/Exiting STOP mode 1. Program the polarity of the trigger event of external wake-up lines by ...
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ST92F120 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 5.11.5 Register Description WAKE-UP CONTROL REGISTER (WUCTRL) R249 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h STOP Bit 2 = STOP: Stop ...
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP MASK REGISTER HIGH (WUMRH) R250 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) 7 WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9 Bit 7:0 = WUM[15:8]: Wake-Up Mask bits. If WUMx ...
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ST92F120 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP TRIGGER REGISTER (WUTRH) R252 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) 7 WUT15 WUT14 WUT13 WUT12 WUT11 WUT10 WUT9 Bit 7:0 = WUT[15:8]: Wake-Up Trigger Polarity ...
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ON-CHIP DIRECT MEMORY ACCESS (DMA) 6.1 INTRODUCTION The ST9 includes on-chip Direct Memory Access (DMA) in order to provide high-speed data transfer between peripherals and memory or Register File. Multi-channel DMA is fully supported by peripher- als having their ...
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ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA) 6.3 DMA TRANSACTIONS The purpose of an on-chip DMA channel is to transfer a block of data between a peripheral and the Register File, or Memory. Each DMA transfer consists of three operations: ...
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DMA TRANSACTIONS (Cont’d) When selecting the DMA transaction with memory, bit DCPR.RM (bit 0 of DCPR) must be cleared. To select between using the ISR or the DMASR reg- ister to extend the address, (see Memory Manage- ment Unit chapter), ...
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ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA) DMA TRANSACTIONS (Cont’d) 6.4 DMA CYCLE TIME The interrupt and DMA arbitration protocol func- tions completely asynchronously from instruction flow. Requests are sampled every 5 CPUCLK cycles. DMA transactions are executed if their ...
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DMA REGISTERS As each peripheral DMA channel has its own spe- cific control registers, the following register list should be considered as a general example. The names and register bit allocations shown here may be different from those found ...
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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU) 7 RESET AND CLOCK CONTROL UNIT (RCCU) 7.1 INTRODUCTION The Reset and Clock Control Unit (RCCU) com- prises two distinct sections: – The Clock Control Unit, which generates and manages the internal ...
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Figure 43. ST92F120 Clock Distribution Diagram Baud Rate Generator SCK Master 1/N N=2,4,16,32 SCK Slave (Max INTCLK/2) SPI EFTx 1...256 MFTx 1...256 WDG P6.5 1...256 STIM P9.6 P6.0 1/8 DIV2 Quartz 0 Oscillator 1/2 1 RCCU ST92F120 - RESET AND ...
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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU) 7.3 CLOCK MANAGEMENT The various programmable features and operating modes of the CCU are handled by four registers: – MODER (Mode Register) This is a System Register (R235, Group E). The input ...
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CLOCK MANAGEMENT (Cont’d) 7.3.1 PLL Clock Multiplier Programming The CLOCK1 signal generated by the oscillator drives a programmable divide-by-two circuit. If the DIV2 control bit in MODER is set (Reset Condi- tion), CLOCK2, is equal to CLOCK1 divided by two; ...
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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK MANAGEMENT (Cont’d) 7.3.3 Peripheral Clock The system clock, INTCLK, which may be the out- put of the PLL clock multiplier, CLOCK2, CLOCK2 CK_AF, is also routed to all ST9 ...
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Figure 46. Example of Low Power mode programming in WFI using CK_AF external clock n PROGRAM FLOW Begin MX(1:0) 00 DX2-0 000 WAIT CSU_CKSEL WFI_CKSEL XTSTOP 1 LPOWFI 1 User’s Program WFI instruction WFI status Interrupt Interrupt Routine XTSTOP 0 ...
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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 47. Example of Low Power mode programming in WFI using CLOCK2/16 n PROGRAM FLOW Begin MX(1:0) DX2-0 WAIT CSU_CKSEL LPOWFI User’s Program WFI instruction WFI status Interrupt Interrupt Routine WAIT CSU_CKSEL ...
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CLOCK CONTROL REGISTERS MODE REGISTER (MODER) R235 - Read/Write System Register Reset Value: 1110 0000 (E0h DIV2 PRS2 PRS1 *Note: This register contains bits which relate to other functions; these are described in the chapter dealing ...
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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK CONTROL REGISTERS (Cont’d) CLOCK FLAG REGISTER (CLK_FLAG) R242 -Read/Write Register Page: 55 Reset Value: 01001000 after a Watchdog Reset Reset Value: 00101000 after a Software Reset Reset Value: 00001000 after a ...
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CLOCK CONTROL REGISTERS (Cont’d) PLL CONFIGURATION REGISTER (PLLCONF) R246 - Read/Write Register Page: 55 Reset Value: xx00x111 (xxh MX1 MX0 - Bits 5:4 = MX[1:0]: PLL Multiplication Factor . Refer to Table 21 for multiplier settings. CAUTION: ...
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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU) 7.5 OSCILLATOR CHARACTERISTICS The on-chip oscillator circuit uses an inverting gate circuit with tri-state output. OSCOUT must not be used to drive external cir- cuits. When the oscillator is stopped, OSCOUT goes ...
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CERAMIC RESONATORS Murata Electronics CERALOCK resonators have been tested with the ST92F120 at 3, 3.68, 4 and 5 MHz. Some resonators have built-in capacitors (see The test circuit is shown in Figure Figure 52. Test Circuit Table 24 shows the ...
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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU) 7.6 RESET/STOP MANAGER The Reset/Stop Manager resets the MCU when one of the three following events occurs: – A Hardware reset, initiated by a low level on the Reset pin. – A ...
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RESET/STOP MANAGER (Cont’d) The on-chip Timer/Watchdog generates a reset condition if the Watchdog mode is enabled (WCR.WDGEN cleared, R252 page 0), and if the programmed period elapses without the specific code (AAh, 55h) written to the appropriate register. The input ...
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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU) 7.7 STOP MODE On ST9 devices provided with an external STOP pin, the Reset/Stop Manager can also stop all os- cillators without resetting the device. To enter STOP Mode, the STOP pin ...
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EXTERNAL MEMORY INTERFACE (EXTMI) 8.1 INTRODUCTION The ST9 External Memory Interface uses two reg- isters (EMR1 and EMR2) to configure external memory accesses. Some interface signals are also affected by WCR - R252 Page 0. If the two registers ...
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ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI) 8.2 EXTERNAL MEMORY SIGNALS The access to external memory is made using the AS, DS, DS2, RW, Port 0, Port1, and WAIT signals described below. Refer to Figure 58 8.2.1 AS: Address Strobe AS ...
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Figure 57. Effects of DS2EN on the behavior of DS and DS2 n SYSTEM CLOCK AS (MC=0) DS2EN=0 OR (DS2EN=1 AND UPPER MEMORY ADDRESSED): DS (MC=0) DS (MC=1, READ) DS (MC=1, WRITE) DS2 DS2EN=1 AND LOWER MEMORY ADDRESSED: DS DS2 ...
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ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY SIGNALS (Cont’d) Figure 58. External Memory Read/Write with a Programmable Wait n NO WAIT CYCLE T1 SYSTEM CLOCK AS (MC=0) ALE (MC=1) P1 ADDRESS DS (MC=0) P0 ADDRESS MULTIPLEXED RW (MC=0) DS ...
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EXTERNAL MEMORY SIGNALS (Cont’d) 8.2.4 RW: Read/Write RW (Alternate Function Output, Active low, Tristate) identifies the type of memory cycle: RW=”1” identifies a memory read cycle, RW=”0” identifies a memory write cycle defined at the beginning of each ...
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ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY SIGNALS (Cont’d) Whenever it is sampled low, the System Clock is stretched and the external memory signals (AS, DS, DS2, RW, P0 and P1) are released in high-im- pedance. The external memory ...
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REGISTER DESCRIPTION EXTERNAL MEMORY REGISTER 1 (EMR1) R245 - Read/Write Register Page: 21 Reset value: 1000 0000 (80h DS2EN ASAF x Bit 7 = Reserved. Bit 6 = MC: Mode Control . 0: AS, DS and ...
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ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY INTERFACE REGISTERS (Cont’d) EXTERNAL MEMORY REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0001 1111 (1Fh) 7 MEM - ENCSR DPRREM LAS1 SEL Bit 7 = Reserved. Bit 6 ...
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EXTERNAL MEMORY INTERFACE REGISTERS (Cont’d) Bits 1:0 = UAS[1:0]: Upper memory address strobe stretch . These two bits contain the number of wait cycles (from add to the System Clock to stretch AS during external upper ...
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ST92F120 - I/O PORTS 9 I/O PORTS 9.1 INTRODUCTION ST9 devices feature flexible individually program- mable multifunctional input/output lines. Refer to the Pin Description Chapter for specific pin alloca- tions. These lines, which are logically grouped as 8-bit ports, can ...
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PORT CONTROL REGISTERS (Cont’d) During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This condition is also held after Reset, except for Ports 0 and 1 in ROM- ...
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ST92F120 - I/O PORTS INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 62. Control Bits Bit 7 PxC2 PxC27 PxC1 PxC17 PxC0 PxC07 n Table 25. Port Bit Configuration Table ( 1... port number) PXC2n 0 PXC1n 0 ...
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INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 63. Basic Structure of an I/O Port Pin PUSH-PULL TRISTATE OPEN DRAIN WEAK PULL-UP OUTPUT SLAVE LATCH ALTERNATE FROM FUNCTION PERIPHERAL OUTPUT INPUT OUTPUT BIDIRECTIONAL OUTPUT MASTER LATCH Figure 64. Input Configuration I/O PIN TRISTATE ...
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ST92F120 - I/O PORTS INPUT/OUTPUT BIT CONFIGURATION (Cont’d) When Px.n is programmed as an Output: (Figure 5) – The Output Buffer is turned Open-drain or Push-pull configuration. – The data stored in the Output Master Latch is ...
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ALTERNATE FUNCTION ARCHITECTURE Each I/O pin may be connected to three different types of internal signal: – Data bus Input/Output – Alternate Function Input – Alternate Function Output 9.5.1 Pin Declared as I/O A pin declared as I/O, is ...
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TIMER/WATCHDOG (WDT) 10 ON-CHIP PERIPHERALS 10.1 TIMER/WATCHDOG (WDT) Important Note: This chapter is a generic descrip- tion of the WDT peripheral. However depending on the ST9 device, some or all of WDT interface signals described may not be connected to ...
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TIMER/WATCHDOG (Cont’d) 10.1.2 Functional Description 10.1.2.1 External Signals The HW0SW1 pin can be used to permanently en- able Watchdog mode. Refer to section 10.1.3.1 on page 126. The WDIN Input pin can be used in one of four modes: – ...
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TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 10.1.2.7 Gated Input Mode This mode can be used for pulse width measure- ment. The Timer is clocked by INTCLK/4, and is started and stopped by means of the input pin and the ST_SP bit. When ...
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TIMER/WATCHDOG (Cont’d) 10.1.3.3 Preventing Watchdog System Reset In order to prevent a system reset, the sequence AAh, 55h must be written to WDTLR (Watchdog Timer Low Register). Once 55h has been written, the Timer reloads the constant and counting re- ...
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TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 10.1.4 WDT Interrupts The Timer/Watchdog issues an interrupt request at every End of Count, when this feature is ena- bled. A pair of control bits, IA0S (EIVR.1, Interrupt A0 se- lection bit) and TLIS (EIVR.2, Top ...
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TIMER/WATCHDOG (Cont’d) 10.1.5 Register Description The Timer/Watchdog is associated with 4 registers mapped into Group F, Page 0 of the Register File. WDTHR: Timer/Watchdog High Register WDTLR: Timer/Watchdog Low Register WDTPR: Timer/Watchdog Prescaler Register WDTCR: Timer/Watchdog Control Register Three additional ...
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TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) Bit 3 = INEN: Input Enable . This bit is set and cleared by software. 0: Disable input section 1: Enable input section Bit 2 = OUTMD: Output Mode. This bit is set and cleared by ...
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STANDARD TIMER (STIM) Important Note: This chapter is a generic descrip- tion of the STIM peripheral. Depending on the ST9 device, some or all of the interface signals de- scribed may not be connected to external pins. For the ...
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STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 10.2.2 Functional Description 10.2.2.1 Timer/Counter control Start-stop Count. The ST-SP bit (STC.7) is used in order to start and stop counting. An instruction which sets this bit will cause the Standard Timer to start ...
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STANDARD TIMER (Cont’d) 10.2.2.4 Standard Timer Output Modes OUTPUT modes are selected using 2 bits of the STC register: OUTMD1 and OUTMD2. No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”) The output is disabled and the corresponding pin is ...
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STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 10.2.5 Register Description COUNTER HIGH BYTE REGISTER (STH) R240 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) 7 ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 Bits 7:0 = ST.[15:8]: Counter High-Byte. COUNTER LOW ...
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EXTENDED FUNCTION TIMER (EFT) 10.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals ...
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EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Figure 73. Timer Block Diagram INTCLK 8 low 8 high 8-bit buffer EXEDG 16 BIT 1/2 FREE RUNNING 1/4 COUNTER 1/8 COUNTER ALTERNATE REGISTER CC1 CC0 OVERFLOW EXTCLK DETECT CIRCUIT ICF1 OCF1 ...
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EXTENDED FUNCTION TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MSB At t0 Other instructions Returns the buffered Read LSB At t0 +Dt LSB value at t0 Sequence ...
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EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Figure 74. Counter Timing Diagram, INTCLK divided by 2 INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF Figure 75. Counter Timing Diagram, INTCLK divided by 4 INTCLK INTERNAL RESET TIMER CLOCK ...
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EXTENDED FUNCTION TIMER (Cont’d) 10.3.3.3 Input Capture In this section, the index may The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free run- ning counter ...
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EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Figure 77. Input Capture Block Diagram ICAP1 EDGE DETECT CIRCUIT2 ICAP2 IC2R 16-BIT 16-BIT FREE RUNNING COUNTER Figure 78. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi ...
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EXTENDED FUNCTION TIMER (Cont’d) 10.3.3.4 Output Compare In this section, the index may This function can be used to control an output waveform or indicating when a period of time has elapsed. When a ...
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EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Figure 79. Output Compare Block Diagram 16 BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit OC2R OC1R Figure 80. Output Compare Timing Diagram, Internal Clock Divided by 2 OUTPUT COMPARE ...
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EXTENDED FUNCTION TIMER (Cont’d) 10.3.3.5 Forced Compare Mode In this section i may represent The following bits of the CR1 register are used: FOLV2 FOLV1 OLVL2 When the FOLV i bit is set, the OLVL i bit ...
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EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) 10.3.3.7 Pulse Width Modulation Mode Pulse Width Modulation mode enables the gener- ation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. ...
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EXTENDED FUNCTION TIMER (Cont’d) 10.3.4 Interrupt Management The interrupts of the Extended Function Timers are mapped on external interrupt channels of the microcontroller (refer to the “Interrupts” chapter). The five interrupt sources (2 input captures, 2 out- put compares and ...
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EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Note: A single access (read/write) to the SR regis- ter at the beginning of the interrupt routine is the first step needed to clear all the EFT interrupt flags second ...
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EXTENDED FUNCTION TIMER (Cont’d) 10.3.5 Register Description Each Timer is associated with three control and one status registers, and with six pairs of data reg- isters (16-bit values) relating to the two input cap- tures, the two output compares, the ...
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EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) COUNTER HIGH REGISTER (CHR) R244 - Read Only Register Page: 28 Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 7 MSB ...
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EXTENDED FUNCTION TIMER (Cont’d) OUTPUT COMPARE 1 (OC1HR) R248 - Read/Write Register Page: 28 Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 ...
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EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) CONTROL REGISTER 1 (CR1) R252 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h) 7 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 Bit 7 = ICIE Input Capture Interrupt Enable. ...
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EXTENDED FUNCTION TIMER (Cont’d) CONTROL REGISTER 2 (CR2) R253 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Enable. 0: Output Compare 1 ...
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EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) STATUS REGISTER (SR) R254 - Read Only Register Page: 28 Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ...
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EXTENDED FUNCTION TIMER (Cont’d) Table 29. Extended Function Timer Register Map Address Register 7 Name (Dec.) IC1HR MSB R240 Reset Value x IC1LR MSB R241 Reset Value x IC2HR MSB R242 Reset Value x IC2LR MSB R243 Reset Value x ...
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EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Table 30. Extended Function Timer Page Map Timer number EFT0 EFT1 154/324 9 Page (hex ...
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MULTIFUNCTION TIMER (MFT) 10.4.1 Introduction The Multifunction Timer (MFT) peripheral offers powerful timing capabilities and features 12 oper- ating modes, including automatic PWM generation and frequency measurement. The MFT comprises a 16-bit Up/Down counter driven by an 8-bit programmable ...
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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) The configuration of each input is programmed in the Input Control Register. Each of the two output pins can be driven from any of three possible sources: – Compare Register 0 logic – Compare ...
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MULTIFUNCTION TIMER (Cont’d) 10.4.2 Functional Description The MFT operating modes are selected by pro- gramming the Timer Control Register (TCR) and the Timer Mode Register (TMR). 10.4.2.1 Trigger Events A trigger event may be generated by software (by setting either ...
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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 10.4.2.8 Free Running Mode The timer counts continuously ( Down mode) and the counter value simply overflows or underflows through FFFFh or zero; there is no End Of Count condition as such, ...
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MULTIFUNCTION TIMER (Cont’d) Every software or external trigger event on REG0R performs a reload from REG0R resetting the Biload cycle. In One Shot mode (reload initiat software external trigger), reloading is always from REG0R. B) ...
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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 10.4.3 Input Pin Assignment The two external inputs (TxINA and TxINB) of the timer can be individually configured to catch a par- ticular external event (i.e. rising edge, falling edge, or both rising and ...
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MULTIFUNCTION TIMER (Cont’d) 10.4.3.1 TxINA = I/O - TxINB = I/O Input pins A and B are not used by the Timer. The counter clock is internally generated and the up/ down selection may be made only by software via ...
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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 10.4.3.9 TxINA = Clock Up - TxINB = Clock Down The edge received on input pin A (or B) performs a one step up (or down) count, so that the counter clock and the ...
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MULTIFUNCTION TIMER (Cont’d) 10.4.3.13 Autodiscrimination Mode The phase between two pulses (respectively on in- put pin B and input pin A) generates a one step up (or down) count, so that the up/down control and the counter clock are both ...
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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 10.4.4 Output Pin Assignment Two external outputs are available when pro- grammed as Alternate Function Outputs of the I/O pins. Two registers Output A Control Register (OACR) and Output B Control Register (OBCR) define ...
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MULTIFUNCTION TIMER (Cont’d) For a configuration where TxOUTA is driven by the Over/Underflow and by Compare 0, and TxOUTB is driven by the Over/Underflow and by Compare 1. OACR is programmed with TxOUTA preset to “0”. OUF sets TxOUTA while ...
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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 10.4.5 Interrupt and DMA 10.4.5.1 Timer Interrupt The timer has 5 different Interrupt sources, be- longing to 3 independent groups, which are as- signed to the following Interrupt vectors: Table 33. Timer Interrupt Structure ...
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MULTIFUNCTION TIMER (Cont’d) Figure 87. Pointer Mapping for Register to Register Transfers Register File 8 bit Counter XXXXXX11 8 bit Addr Pointer XXXXXX10 8 bit Counter XXXXXX01 8 bit Addr Pointer XXXXXX00 10.4.5.4 DMA Transaction Priorities Each Timer DMA transaction ...
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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 10.4.5.6 DMA End Of Block Interrupt Routine An interrupt request is generated after each block transfer (EOB) and its priority is the same as that assigned in the usual interrupt request, for the two ...
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MULTIFUNCTION TIMER (Cont’d) CAPTURE LOAD 0 HIGH REGISTER (REG0HR) R240 - Read/Write Register Page: 10 Reset value: undefined 7 R15 R14 R13 R12 R11 This register is used to capture values from the Up/Down counter or load preset values (MSB). ...
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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) TIMER CONTROL REGISTER (TCR) R248 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 CEN CCP0 CCMP0 CCL UDC UDCS OF0 CS Bit 7 = CEN: Counter enable . This bit is ...
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MULTIFUNCTION TIMER (Cont’d) TIMER MODE REGISTER (TMR) R249 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 OE1 OE0 BM RM1 RM0 ECK REN Bit 7 = OE1: Output 1 enable. 0: Disable the Output 1 (TxOUTB pin) ...
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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) EXTERNAL INPUT CONTROL (T_ICR) R250 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 IN3 IN2 IN1 IN0 A0 Bits 7:4 = IN[3:0]: Input pin function. These bits are set and cleared ...
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MULTIFUNCTION TIMER (Cont’d) OUTPUT A CONTROL REGISTER (OACR) R252 - Read/Write Register Page: 10 Reset value: 0000 0000 7 C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 CEV 0P Bits 7:6 = C0E[0:1]: COMP0 action bits . These bits are set and ...
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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) OUTPUT B CONTROL REGISTER (OBCR) R253 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 OEV 0P Bits 7:6 = C0E[0:1]: COMP0 Action Bits . These ...
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MULTIFUNCTION TIMER (Cont’d) FLAG REGISTER (T_FLAGR) R254 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 CP0 CP1 CM0 CM1 OUF Bit 7 = CP0: Capture 0 flag. This bit is set by hardware after a capture on ...
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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA MASK REGISTER (IDMR) R255 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 GTIEN CP0D CP0I CP1I CM0D CM0I CM1I OUI Bit 7 = GTIEN: Global timer interrupt enable . This ...
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MULTIFUNCTION TIMER (Cont’d) DMA ADDRESS POINTER REGISTER (DAPR) R241 - Read/Write Register Page: 9 Reset value: undefined 7 DAP7 DAP6 DAP5 DAP4 DAP3 DAP2 Bits 7:2 = DAP[7:2]: MSB of DMA address regis- ter location. These are the most significant ...
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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA CONTROL REGISTER (IDCR) R243 - Read/Write Register Page: 9 Reset value: 1100 0111 (C7h) 7 CPE CME DCTS DCTD SWEN PL2 PL1 PL0 Bit 7 = CPE: Capture 0 EOB . This bit ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) 10.5 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) 10.5.1 Introduction The Multiprotocol Serial Communications Inter- face (SCI-M) offers full-duplex serial data ex- change with a wide range of external equipment. The SCI-M offers four operating modes: Asynchro- ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.3 Functional Description The SCI-M has four operating modes: – Asynchronous mode – Asynchronous mode with synchronous clock – Serial expansion mode – Synchronous mode Figure 89. SCI -M Functional ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4 SCI-M Operating Modes 10.5.4.1 Asynchronous Mode In this mode, data and clock can be asynchronous (the transmitter and receiver can use their own clocks to sample received data), each ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.3 Serial Expansion Mode This mode is used to communicate with an exter- nal synchronous peripheral. The transmitter only provides the clock waveform during the period that data is being ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 91. SCI -M Operating Modes DATA START BIT I CLOCK Asynchronous Mode I/O DATA START BIT (Dummy) CLOCK Serial Expansion Mode Note: In all operating modes, the ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.5 Serial Frame Format Characters sent or received by the SCI can have some or all of the features in the following format, depending on the operating mode: START: the ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.5.1 Data transfer Data to be transmitted by the SCI is first loaded by the program into the Transmitter Buffer Register. The SCI will transfer the data into the Transmitter ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 93. Auto Echo Configuration TRANSMITTER RECEIVER All modes except Synchronous Figure 94. Loop Back Configuration TRANSMITTER RECEIVER All modes except Synchronous Figure 95. Auto Echo and Loop-Back Configuration TRANSMITTER ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.6 Clocks And Serial Transmission Rates The communication bit rate of the SCI transmitter and receiver sections can be provided from the in- ternal Baud Rate Generator or from external ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 38. SCI-M Baud Rate Generator Divider Values Example 1 Baud Clock Desired Freq Rate Factor 50. 75. 110. 300. 600.00 16 ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.8 Input Signals SIN: Serial Data Input. This pin is the serial data input to the SCI receiver shift register. TXCLK: External Transmitter Clock Input. This pin is the external ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.10 Interrupts and DMA 10.5.10.1 Interrupts The SCI can generate interrupts as a result of sev- eral conditions. Receiver interrupts include data pending, receive errors (overrun, framing and par- ity), ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 41. SCI-M Interrupt Vectors Interrupt Source Transmitter Buffer or Shift Register Empty Transmit DMA end of Block Received Data Pending Receive DMA end of Block Break Detector Address Word ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.10.2 DMA Two DMA channels are associated with the SCI, for transmit and for receive. These follow the reg- ister scheme as described in the DMA chapter. DMA Reception To ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.11 Register Description The SCI-M registers are located in the following pages in the ST9: SCI-M number 0: page 24 (18h) SCI-M number 1: page 25 (19h) (when present) The ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) RECEIVER DMA COUNTER POINTER (RDCPR) R240 - Read/Write Reset value: undefined 7 RC7 RC6 RC5 RC4 RC3 Bit 7:1 = RC[7:1]: Receiver DMA Counter Pointer. These bits contain the address ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT VECTOR REGISTER (S_IVR) R244 - Read/Write Reset value: undefined Bit 7:3 = V[7:3]: SCI Interrupt Vector Base Ad- dress. User programmable interrupt vector ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT MASK REGISTER (IMR) R246 - Read/Write Reset value: 0xx00000 7 BSN RXEOB TXEOB RXE RXA Bit 7 = BSN: Buffer or shift register empty inter- rupt . This bit ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT STATUS REGISTER (S_ISR) R247 - Read/Write Reset value: undefined RXAP RXBP RXDP TXBEM TXSEM Bit 7 = OE: Overrun Error Pending . This bit is ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) RECEIVER BUFFER REGISTER (RXBR) R248 - Read only Reset value: undefined 7 RD7 RD6 RD5 RD4 RD3 Bit 7:0 = RD[7:0]: Received Data. This register stores the data portion of ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT/DMA PRIORITY REGISTER (IDPR) R249 - Read/Write Reset value: undefined 7 AMEN SB SA RXD TXD Bit 7 = AMEN: Address Mode Enable. This bit, together with the AM bit ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) CHARACTER CONFIGURATION (CHCR) R250 - Read/Write Reset value: undefined PEN AB SB1 Bit 7 = AM: Address Mode . This bit, together with the AMEN bit (in ...