ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 88

• Manufacturer Part Number: ST92F120V1Q7
• Description: Microcontrollers (MCU) Flash 128K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST92F120V1Q7

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 16 Channel
• Lead Free Status / Rohs Status: No

ST92F120 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
WAKE-UP
(WUTRH)
R252 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
Bit 7:0 = WUT[15:8]: Wake-Up Trigger Polarity
Bits
These bits are set and cleared by software.
0: The corresponding WUPx pending bit will be set
1: The corresponding WUPx pending bit will be set
WAKE-UP TRIGGER REGISTER LOW (WUTRL)
R253 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
Bit 7:0 = WUT[7:0]: Wake-Up Trigger Polarity Bits
These bits are set and cleared by software.
0: The corresponding WUPx pending bit will be set
1: The corresponding WUPx pending bit will be set
WARNING
1. As the external wake-up lines are edge trig-
2. If either a rising or a falling edge on the external
88/324
WUT15 WUT14 WUT13 WUT12 WUT11 WUT10 WUT9
9
WUT7
on the falling edge of the input wake-up line .
on the rising edge of the input wake-up line.
on the falling edge of the input wake-up line.
on the rising edge of the input wake-up line.
gered, no glitches must be generated on these
lines.
wake-up
WUTRLH or WUTRL registers, the pending bit
will not be set.
7
7
WUT6
WUT5
lines
TRIGGER
WUT4
occurs
WUT3
REGISTER
while
WUT2
writing
WUT1
HIGH
WUT8
WUT0
0
0
the
WAKE-UP PENDING REGISTER HIGH
(WUPRH)
R254 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
Bit 7:0 = WUP[15:8]: Wake-Up Pending Bits
These bits are set by hardware on occurrence of
the trigger event on the corresponding wake-up
line. They must be cleared by software. They can
be set by software to implement a software inter-
rupt.
0: No Wake-up Trigger event occurred
1: Wake-up Trigger event occured
WAKE-UP PENDING REGISTER LOW (WUPRL)
R255 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
Bit 7:0 = WUP[7:0]: Wake-Up Pending Bits
These bits are set by hardware on occurrence of
the trigger event on the corresponding wake-up
line. They must be cleared by software. They can
be set by software to implement a software inter-
rupt.
0: No Wake-up Trigger event occurred
1: Wake-up Trigger event occured
Note: To avoid losing a trigger event while clear-
ing the pending bits, it is recommended to use
read-modify-write
BAND) to clear them.
WUP15 WUP14 WUP13 WUP12 WUP11 WUP10 WUP9
WUP7
7
7
WUP6
WUP5
instructions
WUP4
WUP3
WUP2
(AND,
WUP1
BRES,
WUP8
WUP0
0
0