ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 264

• Manufacturer Part Number: ST92F120V1Q7
• Description: Microcontrollers (MCU) Flash 128K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST92F120V1Q7

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 16 Channel
• Lead Free Status / Rohs Status: No

J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
IFR2, In-Frame Response Type 2 opcode.
The In-frame Response Type 2 (IFR2) opcode is
set if the user program wants to transmit a physical
address byte (contained in the PADDR register) in
response to a message that is currently being re-
ceived.
The user program decides to set up an IFR2 upon
receiving a certain portion of the data byte string of
an incoming message. No write of the TXDATA
register is required. The IFR gets its data byte from
the PADDR register.
The JBLPD block will enable the transmission of
the IFR2 on these conditions:
– 1) The CRC check is valid (otherwise the CRCE
– 2) The received message length is valid if ena-
– 3) A valid EOD minimum symbol is received (oth-
– 4) If NFL = 0 & Received Byte Count for this
– 5) If not presently executing an MSG, IFR3, op-
– 6) If not presently executing an IFR1, IFR2, or
– 7) If not presently receiving an IFR portion of a
The IFR byte is then attempted according to the
procedure described in section “Transmitting a
type 2 IFR”. Note that if an IFR opcode is written, a
queued MSG or MSG+CRC is overridden by the
IFR2.
IFR3, In-Frame Response Type 3 opcode.
The In-Frame Response Type 3 (IFR3) opcode is
set if the user program wants to initiate to transmit
or continue to transmit a string of data bytes in re-
sponse to a message that is currently being re-
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is set)
bled (otherwise the TRA is set)
erwise the IFD may eventually get set due to byte
synchronization errors)
frame <=11 (otherwise TRA is set)
code (otherwise TRA is set, and TDUF will get
set because the transmit state machine will be
expecting more data, so the inverted CRC will be
appended to this frame)
IFR3+CRC opcodes, otherwise TRA is set (but
no TDUF)
frame, otherwise TRA is set.
ceived.
The IFR3 uses the contents of the TXDATA regis-
ter for data. The user program decides to set up an
IFR3 upon receiving a certain portion of the data
byte string of an incoming message. A previous
write of the TXDATA register should have oc-
curred.
The JBLPD block will enable the transmission of
the first byte of an IFR3 string on these conditions:
– 1) The CRC check is valid (otherwise the CRCE
– 2) The received message length is valid if ena-
– 3) A valid EOD minimum symbol is received (oth-
– 4) If NFL = 0 & Received Byte Count for this
– 5) If not presently executing an MSG opcode
– 6) If not presently executing an IFR1, IFR2, or
– 7) If not presently receiving an IFR portion of a
The IFR3 byte string is then attempted according
to the procedure described in section “Transmit-
ting a type 3 IFR”. Note that if an IFR3 opcode is
written, a queued MSG or MSG+CRC is overrid-
den by the IFR3.
The next byte(s) in the IFR3 data string shall also
be written with the IFR3 opcode except for the last
byte in the string which shall be written with the
IFR3+CRC opcode. Each IFR3 data byte trans-
mission is accomplished with a TXDATA/TXOP
write sequence. The succeeding IFR3 transmit re-
quests will be enabled on conditions 4 and 5 listed
above.
is set)
bled (otherwise the TRA is set)
erwise the IFD may eventually get set due to byte
synchronization errors)
frame <=9 (otherwise TRA is set and inverted
CRC is transmitted due to TDUF)
(otherwise TRA is set, and TDUF will get set be-
cause the transmit state machine will be expect-
ing more data and the inverted CRC will be
appended to this frame)
IFR3+CRC opcode, otherwise TRA is set (but no
TDUF)
frame, otherwise TRA is set.