ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 270

• Manufacturer Part Number: ST92F120V1Q7
• Description: Microcontrollers (MCU) Flash 128K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST92F120V1Q7

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 16 Channel
• Lead Free Status / Rohs Status: No

J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 0 = IBD Invalid Bit Detect.
The IBD bit gets set whenever the receiver detects
that the filtered VPWI pin was not fixed in a state
long enough to reach the minimum valid symbol
time of Tv1 (or 35 µs). Any timing event less than
35 µs (and, of course, > 7 µs since the VPWI digit-
al filter will not allow pulses less than this through
its filter) is considered as noise and sets the IBD
accordingly. At this point the JBLPD peripheral will
cease transmitting and receiving any information
until a valid EOF symbol is received.
IBD errors are inhibited if the JBLPD peripheral is
in the “sleep or filter and NOT presently transmit-
ting” mode. An IBD error occurs once for a frame.
Afterwards, the receiver is disabled until an EOFM
symbol is received, and queued transmits for the
present frame are cancelled (but the TRA bit is not
set).
IBD is cleared when ERROR is read. Note that if
an invalid bit is detected during a bus idle condi-
tion, the IBD flag gets set and a new EOFmin must
be seen after the invalid bit before commencing to
receive again. IBD is also cleared while the CON-
TROL.JE bit is reset or while the CONTROL.JDIS
bit is set and on reset.
0: No invalid bit detected
1: Invalid bit detected
JBLPD INTERRUPT VECTOR REGISTER (IVR)
R248- Read/Write (except bits 2:1)
Register Page: 23
Reset Value: xxxx xxx0 (xxh)
Bit 7:3 = V[7:3] Interrupt Vector Base Address.
User programmable interrupt vector bits.
Bit 2:1 = EV[2:1] Encoded Interrupt Source (Read
Only).
EV2 and EV1 are set by hardware according to the
interrupt source, given in
tus register bits description about the explanation
of the meaning of the interrupt sources)
Table 52. Interrupt Sources
270/324
9
V7
7
EV2
0
0
1
1
V6
V5
EV1
0
1
0
1
V4
Table 8
V3
Interrupt Sources
EODM, EOFM
RDRF, REOB
ERROR, TLA
TRDY, TEOB
EV2
(refer to the Sta-
EV1
0
-
Bit 0 = Reserved.
JBLPD PRIORITY LEVEL REGISTER (PRLR)
R249- Read/Write
Register Page: 23
Reset Value: 0001 0000 (10h)
Bit 7:5 = PRL[2:0] Priority level bits
The priority with respect to the other peripherals
and the CPU is encoded with these three bits. The
value of “0” has the highest priority, the value “7”
has no priority. After the setting of this priority lev-
el, the priorities between the different Interrupt
sources and DMA of the JBLPD peripheral is hard-
ware defined (refer to the “Status register” bits de-
scription, the “Interrupts Management” and the
section about the explanation of the meaning of
the interrupt sources).
Depending
TIONS.DMASUSP bit, the DMA transfers can or
cannot be suspended by an ERROR or TLA event.
Refer to the description of DMASUSP bit.
Table 53. Internal Interrupt and DMA Priorities
without DMA suspend mode
Table 54. Internal Interrupt and DMA Priorities
with DMA suspend mode
PRL2
7
Priority Level
Higher Priority
Priority Level
Higher Priority
Lower Priority
Lower Priority
PRL1
PRL0
on
the
SLP
value
-
Event Sources
Event Sources
EODM, EOFM
EODM, EOFM
RDRF, REOB
RDRF, REOB
ERROR, TLA
TRDY, TEOB
ERROR, TLA
TRDY, TEOB
RX-DMA
RX-DMA
-
TX-DMA
TX-DMA
of
REOBP TEOBP
the
0
OP-