ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 255

• Manufacturer Part Number: ST92F120V1Q7
• Description: Microcontrollers (MCU) Flash 128K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST92F120V1Q7

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 16 Channel
• Lead Free Status / Rohs Status: No

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.8.6.3 DMA Management in Reception Mode
The DMA in reception is performed when the
RDRF bit of the STATUS register is set (by hard-
ware). The RDRF bit is reset as soon as the DMA
cycle is finished.
To enable the DMA feature, the RXD_M bit of the
IMR register must be set (by software).
Each DMA request performs the transfer of a sin-
gle byte from the RXDATA register of the peripher-
al toward Register File or Memory Space
10).
Each DMA transfer consists of three operations
that are performed with minimum use of CPU time:
– A load from the JBLPD data register (RXDATA)
Figure 118. DMA in Reception Mode
to a location of Register File/Memory addressed
JBLPD peripheral
RXDATA
(Figure
J1850 Byte Level Protocol Decoder (JBLPD)
– A post-increment of the DMA Address Register
– A post-decrement of the DMA transaction coun-
Note: When the REOBP pending bit is set (at the
end of the last DMA transfer), the reception DMA
enable bit (RXD_M) is automatically reset by hard-
ware. However, the DMA can be disabled by soft-
ware resetting the RXD_M bit.
Note: The DMA request acknowledge could de-
pend on the priority level stored in the PRLR regis-
ter.
through the DMA Address Register (or Register
pair);
(or Register pair);
ter, which contains the number of transactions
that have still to be performed.
Data received
Previous data
Memory space
Register File
Current
Address
Pointer
or
255/324
9