ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 195

Microcontrollers (MCU) Flash 128K SPI/I2C

ST92F120V1Q7

Manufacturer Part Number
ST92F120V1Q7
Description
Microcontrollers (MCU) Flash 128K SPI/I2C
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST92F120V1Q7

Data Bus Width
8 bit, 16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
77
Number Of Timers
5
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
PQFP-100
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 16 Channel
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST92F120V1Q7
Manufacturer:
ST
Quantity:
6 765
Part Number:
ST92F120V1Q7
Manufacturer:
ST
0
Part Number:
ST92F120V1Q7
Manufacturer:
ST
Quantity:
20 000
Part Number:
ST92F120V1Q7C
Manufacturer:
ST
0
Part Number:
ST92F120V1Q7C
Manufacturer:
ST
Quantity:
20 000
Part Number:
ST92F120V1Q7D/TR
Manufacturer:
ST
0
Part Number:
ST92F120V1Q7DTR
Manufacturer:
MAXIM
Quantity:
2 854
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
INTERRUPT VECTOR REGISTER (S_IVR)
R244 - Read/Write
Reset value: undefined
Bit 7:3 = V[7:3]: SCI Interrupt Vector Base Ad-
dress.
User programmable interrupt vector bits for trans-
mitter and receiver.
Bit 2:1 = EV[2:1]: Encoded Interrupt Source.
Both bits EV2 and EV1 are read only and set by
hardware according to the interrupt source.
Bit 0 = D0: This bit is forced by hardware to 0.
EV2 EV1
V7
0
0
1
1
7
0
1
0
1
V6
Receiver Error (Overrun, Framing, Parity)
Break Detect or Address Match
Received Data Pending/Receiver DMA
End of Block
Transmitter buffer or shift register empty
transmitter DMA End of Block
V5
V4
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
Interrupt source
V3
EV2
EV1
0
0
ADDRESS/DATA COMPARE REGISTER (ACR)
R245 - Read/Write
Reset value: undefined
Bit 7:0 = AC[7:0]: Address/Compare Character .
With either 9th bit address mode, address after
break mode, or character search, the received ad-
dress will be compared to the value stored in this
register. When a valid address matches this regis-
ter content, the Receiver Address Pending bit
(RXAP in the S_ISR register) is set. After the
RXAP bit is set in an addressed mode, all received
data words will be transferred to the Receiver Buff-
er Register.
AC7
7
AC6
AC5
AC4
AC3
AC2
AC1
195/324
AC0
0
9

Related parts for ST92F120V1Q7