ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 281

• Manufacturer Part Number: ST92F120V1Q7
• Description: Microcontrollers (MCU) Flash 128K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST92F120V1Q7

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 16 Channel
• Lead Free Status / Rohs Status: No

ANALOG TO DIGITAL CONVERTER (Cont’d)
Analog channels 6 and 7 monitor an acceptable
voltage level window for the converted analog in-
puts. The external voltages applied to inputs 6 and
7 are considered normal while they remain below
their respective Upper thresholds, and above or at
their respective Lower thresholds.
When the external signal voltage level is greater
than, or equal to, the upper programmed voltage
limit, or when it is less than the lower programmed
voltage limit, a maskable interrupt request is gen-
erated and the Compare Results Register is up-
dated in order to flag the threshold (Upper or Low-
er) and channel (6 or 7) responsible for the inter-
rupt. The four threshold voltages are user pro-
grammable in dedicated registers (08h to 0Bh) of
the A/D register page. Only the 4 MSBs of the
Compare Results Register are used as flags (the 4
LSBs always return “1” if read), each of the four
MSBs being associated with a threshold condition.
Following a hardware reset, these flags are reset.
During normal A/D operation, the CRR bits are set,
in order to flag an out of range condition and are
automatically reset by hardware after a software
reset of the Analog Watchdog Request flag in the
AD_ICR Register.
Figure 122. A/D Trigger Source
n
EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D)
10.9.2.4 Power Down Mode
Before enabling an A/D conversion, the POW bit of
the Control Logic Register must be set; this must
be done at least 60µs before the first conversion
start, in order to correctly bias the analog section
of the converter circuitry.
When the A/D is not required, the POW bit may be
reset in order to reduce the total power consump-
tion. This is the reset configuration, and this state
is also selected automatically when the ST9 is
placed in Halt Mode (following the execution of the
halt instruction).
Upper threshold
Lower threshold
Analog Voltage
(Window Guarded)
Normal Area
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