ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 43

• Manufacturer Part Number: ST92F120V1Q7
• Description: Microcontrollers (MCU) Flash 128K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST92F120V1Q7

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 16 Channel
• Lead Free Status / Rohs Status: No

REGISTER DESCRIPTION (Cont’d)
When in Erase Suspend the memory accepts only
the following operations: Read, Erase Resume
and Byte Program. Updating the EEPROM memo-
ry is not possible during a Flash Erase Suspend.
The FSUSP bit must be reset (and FWMS must be
set again) to resume a suspended Sector Erase
operation.
0: Resume sector erase when FWMS is set again.
1: Suspend Sector erase
Bit 1 = PROT: Set Protection (Read/Write).
This bit must be set to select the Set Protection op-
eration. The Set Protection operation allows “0”s in
place of “1”s to be programmed in the four Non
Volatile Protection registers. From 1 to 4 bytes can
be entered (in any order, no need for an ordered
address sequence) before starting the execution
by setting the FWMS bit . Data to be programmed
and addresses in which to program must be pro-
vided (through an LD instruction, for example).
Protection contained in addresses that are not en-
tered are left unchanged. This bit is automatically
reset at the end of the Set Protection operation.
0: Deselect protection
1: Select protection
Bit 0 = FBUSY: Flash Busy (Read Only).
This bit is automatically set during Page Program,
Byte Program, Sector Erase or Set Protection op-
erations when the first address to be modified is
latched in Flash memory, or during Chip Erase op-
eration when bit FWMS is set. When this bit is set
every read access to the Flash memory will output
invalid data (FFh equivalent to a NOP instruction),
while every write access to the Flash memory will
be ignored. At the end of the write operations or
during a Sector Erase Suspend, this bit is auto-
matically reset and the memory returns to read
mode. After an Erase Resume this bit is automati-
cally set again. The FBUSY bit remains high for a
maximum of 10 s after Power-Up and when exit-
ing Power-Down mode, meaning that the Flash
memory is not yet ready to be accessed.
0: Flash not busy
1: Flash busy
ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
EEPROM CONTROL REGISTER (ECR)
Address: 224001h - Read/Write
Reset value: 000x x000 (xxh)
The EEPROM Control Register is used to enable
all the operations for the EEPROM memory in de-
vices with EEPROM hardware emulation.
The ECR also contains two bits (WFIS and FEIEN)
that are related to both Flash and EEPROM mem-
ories.
Bit 7 = EWMS: EEPROM Write Mode Start .
This bit must be set to start every write/erase oper-
ation in the EEPROM memory. At the end of the
write/erase operation this bit is automatically reset.
Resetting by software this bit does not stop the
current write operation.
0: No effect
1: Start EEPROM write
Bit 6 = EPAGE: EEPROM page update.
This bit must be set to select the Page Update op-
eration in EEPROM memory. The Page Update
operation allows to write a new content: both “0”s
in place of “1”s and “1”s in place of “0”s. From 1 to
16 bytes can be entered (in any order, no need for
an ordered address sequence) before starting the
execution by setting bit EWMS. All the addresses
must belong to the same page (only the 4 LSBs of
address can change). Data to be programmed and
addresses in which to program must be provided
(through an LD instruction, for example). Data
contained in page addresses that are not entered
are left unchanged. This bit is automatically reset
at the end of the Page Update operation.
0: Deselect page update
1: Select page update
Bit 5 = ECHIP: EEPROM chip erase.
This bit must be set to select the Chip Erase oper-
ation in the EEPROM memory. The Chip Erase
operation allows to erase all the EEPROM loca-
tions to (E0 and E1 sectors) FFh. The execution
starts by setting bit EWMS. This bit is automatical-
ly reset at the end of the Chip Erase operation.
0: Deselect chip erase
1: Select chip erase
Bit 4:3 = Reserved.
EWM
7
S
EPAG
E
6
ECHI
P
5
4
3
WFIS
2
FEIE
N
1
43/324
EBUS
Y
0
9