ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 272

• Manufacturer Part Number: ST92F120V1Q7
• Description: Microcontrollers (MCU) Flash 128K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST92F120V1Q7

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 16 Channel
• Lead Free Status / Rohs Status: No

J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 5 = RDRF_M Receive Data Register Full Inter-
rupt Mask bit.
This bit enables the “receive data register full” in-
terrupt source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: RDRF interrupt source masked
1: RDRF interrupt source un-masked
Bit 4 = TLA_M Transmitter Lost Arbitration Inter-
rupt Mask bit.
This bit enables the “transmitter lost arbitration” in-
terrupt source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: TLA interrupt source masked
1: TLA interrupt source un-masked
Bit 3 = RXD_M Receiver DMA Mask bit.
If this bit is “0” no receiver DMA request will be
generated, and the RDRF bit, in the Status Regis-
ter (STATUS), can request an interrupt. If RXD_M
bit is set to “1” then the RDRF bit can request a
DMA transfer. RXD_M is reset by hardware when
the transaction counter value decrements to zero,
that is when a Receiver End Of Block condition oc-
curs (REOBP flag set).
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: Receiver DMA disabled
1: Receiver DMA enabled
Bit 2 = EODM_M End of Data Minimum Interrupt
Mask bit.
This bit enables the “end of data minimum” inter-
rupt source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: EODM interrupt source mask
1: EODM interrupt source un-masked
Bit 1 = EOFM_M End of Frame Minimum Interrupt
Mask bit.
This bit enables the “end of frame minimum” inter-
rupt source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: EOFM interrupt source masked
1: EOFM interrupt source un-masked
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9
Bit 0 = TXD_M Transmitter DMA Mask bit.
If this bit is “0” no transmitter DMA request will be
generated, and the TRDY bit, in the Status Regis-
ter (STATUS), can request an interrupt. If TXD_M
bit is set to “1” then the TRDY bit can request a
DMA transfer. TXD_M is reset by hardware when
the transaction counter value decrements to zero,
that is when a Transmitter End Of Block condition
occurs (TEOBP flag set).
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: Transmitter DMA disabled
1: Transmitter DMA enabled
JBLPD OPTIONS AND REGISTER GROUPS
SELECTION REGISTER (OPTIONS)
R251- Read/Write
Register Page: 23
Reset Value: 0000 0000 (00h)
Bit 7 = INPOL VPWI Input Polarity Selector.
This bit allows the selection of the polarity of the
RX signal coming from the transceivers. Depend-
ing on the specific transceiver, the RX signal is in-
verted or not inverted respect the VPWO and the
J1850 bus line.
0: VPWI input is inverted by the transceiver with
1: VPWI input is not inverted by the transceiver
Bit 6 = NBSYMS NB Symbol Form Selector.
This bit allows the selection of the form of the Nor-
malization Bits (NB0/NB1).
0: NB0 active long symbol (Tv2), NB1 active short
1: NB0 active short symbol (Tv1), NB1 active long
INPOL NBSYMS DMASUSP LOOPB RSEL3 RSEL2 RSEL1 RSEL0
7
respect to the J1850 line.
with respect to the J1850 line.
symbol (Tv1)
symbol (Tv2)
0