st92f120 STMicroelectronics, st92f120 Datasheet
st92f120
Manufacturer Part Number
st92f120
Description
8/16-bit Flash Mcu Family With Ram, Eeprom And J1850 Blpd
Manufacturer
STMicroelectronics
Datasheet
1.ST92F120.pdf
(324 pages)
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DEVICE SUMMARY
September 2002
FLASH - bytes
RAM - bytes
E3PROM - bytes
Network Interface
Temp. Range
Packages
Memories
– Internal Memory: up to 128 Kbytes Single
– 224 general purpose registers (register file)
Clock, Reset and Supply Management
– Register-oriented 8/16 bit CORE with RUN,
– 0-24 MHz Operation (internal Clock), 4.5 - 5.5
– PLL Clock Generator (3-5 MHz crystal)
– Min. instruction time: 83 ns (24 MHz int.
Interrupt Management
– 77 I/O pins
– 4 external fast interrupts + 1 NMI
– Up to 16 pins programmable as wake-up or
Timers
– 16-bit Timer with 8 bit Prescaler, able to be
– 16-bit Standard Timer that can be used to
– Two 16-bit independent Extended Function
– Two 16-bit Multifunction Timers, with Prescal-
Features
Voltage FLASH, 2 to 4 Kbytes RAM, 1K byte
emulated EEPROM (E3PROM
available as RAM, accumulators or index
pointers
WFI, SLOW, HALT and STOP modes
Volt voltage range
clock)
additional external interrupt with multi-level in-
terrupt handler
used as a Watchdog Timer with a large range
of service time (HW/SW enabling through
dedicated pin)
generate a time base independent of PLL
Clock Generator
Timers (EFTs) with Prescaler, 2 Input Cap-
tures and two Output Compares
er, 2 Input Captures and 2 Output Compares
ST92F120V9
--
TM
WITH RAM, EEPROM AND J1850 BLPD
60K
)
2K
ST92F120JV9
-40
J1850
o
C to 105
8/16-BIT FLASH MCU FAMILY
PQFP100
– 2 Serial Communication Interfaces with asyn-
– Serial Peripheral Interface (SPI) with Selecta-
– J1850 Byte Level Protocol Decoder (JBLPD)
– Full I²C multiple Master/Slave Interface sup-
– Rich Instruction Set with 14 Addressing
– Division-by-zero trap generation
– Versatile Development Tools, including As-
Communication Interfaces
8-bit Analog to Digital Converter allowing up
to 16 input channels
DMA
overhead
Instruction Set
Development Tools
o
C or -40
chronous and synchronous capabilities. Soft-
ware Management and synchronous mode
supported
ble Master/Slave mode
(on J versions only)
porting Access Bus
Modes
sembler,
Source Level Debugger, Hardware Emulators
and Real Time Operating System
1K
Controller
o
ST92F120V1
C to 85
Linker,
--
o
C
PQFP100
for
C-Compiler,
128K
4K
ST92F120
reduced
ST92F120JV1
J1850
DATASHEET
processor
Archiver,
Rev. 2.6
1/324
9
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