DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 99

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

Chapter 2: Arria GX Architecture
I/O Structure
Programmable Pull-Up Resistor
Advanced I/O Standard Support
© December 2009 Altera Corporation
f
For the specific sustaining current driven through this resistor and overdrive current
used to identify the next-driven input level, refer to the
chapter.
Each Arria GX device I/O pin provides an optional programmable pull-up resistor
during user mode. If you enable this feature for an I/O pin, the pull-up resistor
(typically 25 k) holds the output to the V
Arria GX device IOEs support the following I/O standards:
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3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
3.3-V PCI-X mode 1
LVDS
LVPECL (on input and output clocks only)
Differential 1.5-V HSTL class I and II
Differential 1.8-V HSTL class I and II
Differential SSTL-18 class I and II
Differential SSTL-2 class I and II
1.2-V HSTL class I and II
1.5-V HSTL class I and II
1.8-V HSTL class I and II
SSTL-2 class I and II
SSTL-18 class I and II
CCIO
level of the output pin’s bank.
DC & Switching Characteristics
Arria GX Device Handbook, Volume 1
2–93