DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 224

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

4–102
Table 4–115. High-Speed I/O Specifications (Part 2 of
Arria GX Device Handbook, Volume 1
DPA lock time
Notes to
(1) When J = 4 to 10, the SERDES block is used.
(2) When J = 1 or 2, the SERDES block is bypassed.
(3) The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150  input clock frequency × W  1,040.
(4) The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource
(global, regional, or local) used. The I/O differential buffer and input register do not have a minimum toggle rate.
Table
Symbol
4–115:
Miscellaneous
Parallel Rapid
Standard
SPI-4
I/O
Training Pattern
000000000011
Conditions
11111111
00001111
10010000
10101010
01010101
2)Note (1), (2)
Transition
Density
100%
10%
25%
50%
—
Min
256
256
256
256
256
Chapter 4: DC and Switching Characteristics
–6 Speed Grade
© December 2009 Altera Corporation
Typ
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High-Speed I/O Specifications
Max
—
—
—
—
—
—
Number of
repetitions
Units