DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 171
DK-DEV-1AGX60N
Manufacturer Part Number
DK-DEV-1AGX60N
Description
KIT DEV ARRIA GX 1AGX60N
Manufacturer
Altera
Series
Arria GXr
Type
FPGAr
Datasheet
1.EP1AGX20CF484C6N.pdf
(234 pages)
Specifications of DK-DEV-1AGX60N
Contents
Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
For Use With/related Products
1AGX60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2372
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 171 of 234
- Download datasheet (4Mb)
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 4 of 4)
© December 2009 Altera Corporation
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
3.3-V PCI
3.3-V PCI-X
LVDS
I/O Standard
Strength
10 mA
12 mA
16 mA
18 mA
20 mA
Drive
6 mA
8 mA
—
—
—
Table 4–58
should be added to GCLK values. These adder values are used to determine I/O
timing when the I/O pin is driven using the regional clock. This applies for all I/O
standards supported by Arria GX with general purpose I/O pins.
Table 4–58
devices.
Table 4–58. EP1AGX35 Row Pin Delay Adders for Regional Clock
RCLK input adder
RCLK PLL input
adder
RCLK output adder
RCLK PLL output
adder
Parameter
GCLK PLL
GCLK PLL
GCLK PLL
GCLK PLL
GCLK PLL
GCLK PLL
GCLK PLL
GCLK PLL
GCLK PLL
GCLK PLL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
through
describes row pin delay adders when using the regional clock in Arria GX
Table 4–59
Parameter
Industrial
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
–0.126
–0.011
0.126
0.011
list EP1AGX35 regional clock (RCLK) adder values that
Fast Corner
Industrial
2.633
1.188
2.615
1.170
2.615
1.170
2.609
1.164
2.596
1.151
2.599
1.154
2.601
1.156
2.755
1.313
2.755
1.313
3.621
2.190
Commercial
Fast Corner
–0.126
–0.011
0.126
0.011
Commercial
2.633
1.188
2.615
1.170
2.615
1.170
2.609
1.164
2.596
1.151
2.599
1.154
2.601
1.156
2.755
1.313
2.755
1.313
3.621
2.190
–6 Speed Grade
–0.281
–0.018
Arria GX Device Handbook, Volume 1
0.281
0.018
–6 Speed
Grade
5.641
2.529
5.643
2.531
5.645
2.533
5.643
2.531
5.455
2.343
5.465
2.353
5.478
2.366
5.791
2.685
5.791
2.685
6.969
3.880
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4–49
Related parts for DK-DEV-1AGX60N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: